Serial bus bridging method and serial bus system

A technology of serial bus and serial peripheral interface, which is applied in the field of serial bus bridging method and serial bus system, can solve the occupation of the IO pins of the main control CPU, cannot realize the function of the slave device, and the main control CPU does not support From the equipment mode and other issues, to achieve the effect of stable reliability and high transmission efficiency

Active Publication Date: 2017-10-27
GENEW TECH
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Problems solved by technology

[0003] However, when the device connected to the master CPU through the serial peripheral interface can only be the master device, the master CPU can only be the slave device
However, the existing main control CPU generally does not support the slave device mode, and the IO pins of the main control CPU may be occupied and cannot realize the slave device function

Method used

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  • Serial bus bridging method and serial bus system
  • Serial bus bridging method and serial bus system
  • Serial bus bridging method and serial bus system

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Embodiment Construction

[0034] The present invention provides a serial bus bridging method and a serial bus system. In order to make the purpose, technical solution and effect of the present invention clearer and clearer, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0035] Those skilled in the art will understand that unless otherwise stated, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the word "comprising" used in the description of the present invention refers to the presence of said features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, Integers, steps, operations, elements, components, and / or groups ...

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Abstract

The invention discloses a serial bus bridging method and a serial bus system. The method comprises the steps that when a master controller accesses a serial peripheral interface host device, a CPLD detects a CS signal and a CLK signal of the serial peripheral interface host device; when it is detected that the CS signal is valid, the CPLD sends an IRQ interrupt signal to the master controller to drive the master controller to write to-be-sent data into a transmitter register; the to-be-sent data is sent to the serial peripheral interface host device piece by piece every time a rising edge is detected; after sending of the to-be-sent data is completed, an IRQ interrupt signal is sent to the master controller to drive the master controller to write a next piece of to-be-sent data into the transmitter register; and the steps are repeated till it is detected that the CS signal is invalid. According to the serial bus bridging method and the serial bus system, communication between host devices is realized through CPLD switchover, transmission efficiency is high, and reliability is stable.

Description

technical field [0001] The invention relates to the technical field of serial bus, in particular to a serial bus bridging method and a serial bus system. Background technique [0002] Serial peripheral buses are widely used in embedded devices, and are generally used for communication of slow devices, with clock frequencies generally below a few megahertz. The serial peripheral bus system is divided into a master device and a slave device for point-to-point communication. The master device generates a clock signal, and the slave device uses the clock of the master device to send and receive data. The host is an embedded master CPU, and the slaves are other peripheral chips. [0003] However, when the device connected to the master CPU through the serial peripheral interface can only be the master device, the master CPU can only be the slave device. However, the existing main control CPU generally does not support the slave device mode, and the IO pins of the main control C...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/24G06F13/38
CPCG06F13/24G06F13/385
Inventor 李小军孟庆晓秦金昆
Owner GENEW TECH
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