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A device for implementing ebr1553 bus protocol based on fpga

A bus protocol, hub technology, applied in the field of simulation and testing, bus communication, can solve problems such as reducing efficiency, increasing the cost and complexity of simulation and testing

Active Publication Date: 2020-03-20
成都旋极历通信息技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the actual bus simulation and testing process, the single-function EBR1553 protocol stack product needs to build a complex network environment according to the EBR1553 star topology, which increases the cost and complexity of simulation and testing, and reduces efficiency

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  • A device for implementing ebr1553 bus protocol based on fpga

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Embodiment Construction

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0016] refer to figure 1 , is a schematic structural diagram of an FPGA-based EBR1553 bus protocol implementation device according to an embodiment of the present invention. The EBR1553 bus protocol implementation device of the present embodiment includes a host interface module 1, a BM recording module 2, a scheduling module 3, a message sending control module 4, a message processing module 5, a logic hub control module 6, an encoding module 7 and a decoding ...

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Abstract

The invention discloses an EBR1553 bus protocol implementation device based on FPGA. The device comprises a host interface module, a BM recording module, a scheduling module, a message sending controlmodule, a message processing module, a logic line concentration control module, a coding module and a decoding module. The modules completely use internal logic of the FPGA to achieve a protocol stack with BC, 31 RT and BM functions which are specified by EBR1553 and can be integrated. According to the device provided by the invention, the multifunctional EBR1553 protocol stack can be achieved byusing the FPGA, and thus simulation and test costs and complexities can be reduced.

Description

technical field [0001] The invention relates to the technical fields of bus communication, simulation and testing, in particular to an FPGA-based EBR1553 bus protocol realization device. Background technique [0002] In order to meet the needs of increased avionics complexity, improved real-time performance, and increased transmission rate, the US SAE organization formulated the EBR1553 bus protocol on the basis of the MIL-STD-1553B standard. The bus protocol uses a star topology and employs a subset of MIL-STD-1553B messages, also consisting of BC (Bus Controller), RT (Remote Terminal) and BM (Bus Monitor). At present, the functions of EBR1553 protocol stack products can only realize a single function, that is, one of BC, a limited number of RT and BM can be realized in time-sharing. In the actual bus simulation and testing process, using a single-function EBR1553 protocol stack product requires building a complex network environment according to the EBR1553 star topology,...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/40H04L12/24H04L12/26
Inventor 何建樑陈卓张泽渺
Owner 成都旋极历通信息技术有限公司