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One time programmable memory implemented using mram stack design

A memory and memory array technology, applied in static memory, read-only memory, digital memory information, etc., can solve problems such as increased cost of integration and difficulty in MTJ stacking

Active Publication Date: 2022-01-04
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, while MRAM is very versatile, it is difficult to design an MTJ stack that can excel in all performance requirements
There is a way to use different stacks for different programs, but the cost of integration will increase significantly

Method used

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  • One time programmable memory implemented using mram stack design
  • One time programmable memory implemented using mram stack design
  • One time programmable memory implemented using mram stack design

Examples

Experimental program
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Embodiment Construction

[0037] In order to meet the requirement that an integrated circuit having at least one array of magnetic one-time programmable memory cells and at least one array of MRAM cells can be integrated with digital and / or analog functional circuit blocks, a single MTJ stack and gated MOS transistor is constructed as To achieve at least two different types of memory. The MTJ stack will be optimized for its primary application (whether it is high-speed working memory, high-density memory or long-term data retention memory), and the basic layout of gated MOS transistors is the same as the magnetic memory cell type. 2a, 2b, 2c and 2d are schematic diagrams of a magnetic random access memory cell. As shown in Figures 2a and 2b, the MRAM cell 105 has an MTJ stack 110 connected in series with a gated MOS transistor M1. The first electrode connects the free magnetic layer 106 of the MTJ stack 110 to the true bit line 100 . The true bit line 100 connects the MRAM cell 105 to a column decode...

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Abstract

An integrated circuit includes a magnetic OTP memory array formed by a plurality of magnetic OTP memory cells, and the magnetic OTP memory cell has an MTJ stack including a fixed magnetic layer, a tunnel barrier insulating layer, a free magnetic layer and a second electrode. When a voltage is applied across the magnetic OTP memory cell, the resistance of the MTJ stack and the gated transistor forms a voltage divider to apply a large voltage across the MTJ stack to break down the tunnel barrier layer and short the pinned layer to the free layer. The integrated circuit has multiple MRAM arrays configured such that the performance and density standards of each of the multiple MRAM arrays match MOS transistor-based memories, including SRAM, DRAM, and flash memory. An integrated circuit may include functional logic units interfaced with a magnetic OTP memory array and an MRAM array for providing digital data storage.

Description

[0001] This application claims priority under 35 U.S.C. §119 to U.S. Provisional Application No. 62 / 142,591 filed April 3, 2015, assigned to a common assignee, and incorporated herein by reference in this article. technical field [0002] The present invention relates to a magnetic random access memory (MRAM) cell incorporated in an array. More particularly, the present invention relates to a one-time programmable (OTP) MRAM cell that can be embedded in an array along with other multi-time programmable MRAM types. Background technique [0003] The rapid increase in the capacity of on-chip memory in recent years has renewed the search for a general-purpose embedded memory technology that combines fast read / write, low-voltage operation, low power consumption, non-volatility, unlimited endurance, and compatibility with CMOS processes. compatibility. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has been considered a promising candidate since its incept...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/16G11C11/409H01L43/12G11C17/02G11C17/16G11C17/18G11C11/00G11C11/419H01L27/22
CPCG11C11/005G11C11/161G11C17/16G11C2213/71G11C11/1659G11C11/1673G11C11/1675G11C17/02H10B61/22H10N50/01G11C11/409G11C11/419G11C17/18
Inventor 诺真·杰王柏刚李元仁朱健刘焕龙
Owner TAIWAN SEMICON MFG CO LTD