OSD architecture for realizing real-time block truncation coding through utilization of line cache area

Abstract

The invention discloses OSD architecture for realizing real-time block truncation coding through utilization of a line cache area. The OSD architecture is characterized by comprising a 4Bit Serial NorFlash, a block truncation coding image decoding module, an OSD module and an LCD output module. The 4Bit Serial Nor Flash is used for storing data. After pixels in an image are decoded, an output format is RGB888. The block truncation coding image decoding module is used for decoding specific pixels in the image in real time through utilization of the line cache area. The OSD module is used for displaying the image of any size at any position of a display area. The pixel data output by the LCD output module comes from the image stored in the 4Bit Serial Nor Flash. The OSD architecture has theadvantages that according to an algorithm and a unit format, real-time decoding for OSD can be finished under a hardware demand of employing the line cache area, so the OSD architecture is very applicable to a single chip system; and moreover, the deficiency possibly existing in the image quality after the decoding is carried out according to a traditional image compression algorithm based on block coding is improved, so the image quality of certain degree and the saving in a hardware aspect can be taken into consideration at the same time.

Description

technical field [0001] The invention relates to the technical field of picture compression, in particular to an OSD architecture for realizing real-time block decoding with a line buffer. Background technique [0002] Today, computer graphics is ubiquitous in a variety of different systems, from expensive calculators to fairly cheap single-chip systems, with support for texture mapping and other technologies. In the process of constructing this type of system, two key technical issues must be considered; first, the storage cost of image textures in memory, due to the cost of RAM, in general systems we hope to reduce as much as possible For memory usage, if a typical 32bit / per pixel is used to store RGBA pixels, the memory will be full quickly. Second, the problem of data transmission, because it is a real-time system, image data is constantly entering and exiting the frame buffer, which can be regarded as a FIFO, so memory bandwidth can easily become the bottleneck of trans...

AI Technical Summary

Problems solved by technology

In the process of constructing this type of system, two key technical issues must be considered; first, the storage cost of image textures in memory, due to the cost of RAM, in general systems we hope to reduce as much as possible Memory usage, if you use a typical 32bit / per pixel to store RGBA pixels, the memory will be full quickly

Second, the problem of data transmission, because it is a real-time system, the image data is constantly entering and exiting the frame buffer, which can be regarded as a FIFO, so the memory bandwidth can easily become the bottleneck of the transmission speed

[0005] However, in the existing algorithms designed based on block coding, most of them use 4x4 pixels as a block for coding and decoding. This structure is not suitable for single-chip systems that only have line buffers and require real-time system execution. to use, or too complex encoding and decoding steps can not be completed in real time, and the more direct block encoding may not achieve the ideal picture quality

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