A fpga-based radar digital pulse compression method to remove DC
A digital pulse and DC removal technology, applied in the field of radar, can solve the problem of inability to achieve DC removal, and achieve the effect of occupying less hardware resources, ensuring computing efficiency, and occupying less memory
Active Publication Date: 2021-04-20
BEIJING HUAHANG RADIO MEASUREMENT & RES INST
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Problems solved by technology
The problem with the scheme is that when N is not the case where the number of FFT points can be obtained, in this case, the method needs to fill the entire sequence with M zeros, so that N+M is an integer power of 2, and a direct current is obtained. The component is X(0) / N+M instead of X(0) / N, which cannot achieve the effect of removing DC
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[0033] Preferred embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the application and are used together with the embodiments of the present invention to explain the principle of the present invention.
[0034] A specific embodiment of the present invention discloses a method for removing direct current by compressing radar digital pulses based on FPGA, such as figure 2 shown, including the following steps:
[0035] Step S1, determine the sequence length of the input signal sig, and generate a ones signal of a sequence length equal to the input signal sequence, all of which are 1s;
[0036] The input signal is the sig signal before pulse compression, which contains a DC component, expressed as the sum of the DC component and the AC component, that is: where X(n) is expressed as a DC component, Expressed as the AC component, f i Indicates the frequ...
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The invention proposes a method for compressing radar digital pulses based on FPGA to remove DC. When inputting a sequence sig, the synchronized input length is the same as the all-one sequence Ones of the input sequence; FFT operation is performed on the input sequence and the all-ones sequence at the same time; The input sequence is accumulated and averaged; the average result of the input sequence is multiplied by the result of the all-one sequence FFT and then subtracted from the FFT result of the input sequence sig to obtain the result of removing the DC component. The invention only needs 1 bit input, occupies little memory; does not introduce extra delay, occupies less hardware resources, and can effectively ensure operation efficiency; through reasonable selection of the implementation method, the performance indicators such as the calculation speed of pulse compression and the occupation of hardware resources can be achieved To achieve the optimum, it can be widely used in modern radar signal processing.
Description
technical field [0001] The invention belongs to the field of radar, and in particular relates to an FPGA-based radar digital pulse compression method for removing direct current. Background technique [0002] With the rapid development of contemporary radar system and technology, the range of radar detection, the minimum resolution of the target distance and the measurement accuracy are all key performance indicators to measure the radar system. Through digital pulse compression technology, the wide pulse signal is compressed into a narrow pulse for processing. This not only satisfies the detection range of the radar but also improves the radar operating range and distance resolution. Pulse compression is also called matched filtering. With the development of modern high-resolution radar technology, digital pulse compression technology is widely used in current radar signal processing. In radar signal processing, in order to achieve a good processing effect, it is necessary...
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IPC IPC(8): G01S13/28G01S7/292
CPCG01S7/2923G01S13/28
Inventor 李长存张辉尹珏玮高嵩赵晓明付常焜
Owner BEIJING HUAHANG RADIO MEASUREMENT & RES INST