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Semiconductor wafer with scribe line conductor and associated method

A semiconductor and dicing groove technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device components, semiconductor/solid-state device testing/measurement, etc., and can solve the problem of time-consuming wafer-level integrated circuit testing

Pending Publication Date: 2018-07-10
ANALOG DEVICES GLOBAL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, wafer-level integrated circuit testing can be a time-consuming process

Method used

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  • Semiconductor wafer with scribe line conductor and associated method
  • Semiconductor wafer with scribe line conductor and associated method
  • Semiconductor wafer with scribe line conductor and associated method

Examples

Experimental program
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Embodiment Construction

[0019] figure 1 is an explanatory diagram showing a portion of a wafer 100 including a large number of integrated circuits (ICs) 102 arranged in a two-dimensional grid pattern, with scribe trenches 104, 106 defining boundaries between the ICs. The plurality of first scribe grooves 104 extend parallel to a first axis (eg, a horizontal x-axis), and a plurality of second scribe grooves extend parallel to a second axis (eg, a vertical y-axis) 106 that is perpendicular to the first axis. The first scribe trenches 104 and the second scribe trenches 106 define a two-dimensional scribe trench grid pattern, wherein each IC 102 is bounded by two first scribe trenches 104 and two second scribe trenches 106 . During wafer level testing, power, control and reference signals generated by off-chip test equipment (not shown) propagate through scribe trenches 104 and / or scribe trenches 106 to reach all ICs 100 on the wafer.

[0020] In some embodiments, the scribe trenches 104, 106 comprise e...

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PUM

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Abstract

A semiconductor wafer with a scribe line conductor and an associated method are provided. The semiconductor wafer is provided that includes at least two integrated circuits (ICs); a scribe line extending adjacent to the at least two ICs; and a first conductor extending within the scribe line and electrically coupled to the at least two ICs.

Description

Background technique [0001] During integrated circuit fabrication, a large number of integrated circuit (IC) dies are formed on a single semiconductor wafer. The ICs are arranged in a grid pattern with scribe grooves running between them. After ICs are fabricated on a semiconductor wafer, the wafer is diced along dicing grooves through a process called "dicing" to separate the individual ICs for subsequent packaging. [0002] Several levels of testing are performed during the IC manufacturing process. Wafer-level process control testing is performed on test circuits to test whether the IC manufacturing process actually produces circuits that meet the requirements of the manufacturing process. Process control test circuits are typically formed in scribe trenches for manufacturing process testing. For example, process control test circuits typically include test transistor devices formed within scribe trenches. Wafer level IC testing is performed on individual ICs before dic...

Claims

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Application Information

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IPC IPC(8): H01L21/66
CPCH01L22/34H01L2223/54493G01R31/2644G01R31/2818H01L22/32H01L23/544H01L22/14
Inventor J·J·欧唐纳C·G·莱登S·吉尔里J·E·D·赫维茨B·伯克莱
Owner ANALOG DEVICES GLOBAL