Stacked silicon package assembly with stiffener

Abstract

A chip package assembly (100, 200, 300, 400) utilizing a stiffener (154, 254, 454, 500, 710, 810, 1110) to improve a package substrate (122) to prevent out-of-plane deformation and A method (1400) for manufacturing the chip package assembly. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die (114), and a stiffener. The packaging substrate has a first surface (102) and a second surface (104) coupled by a sidewall (106). The at least one IC die is disposed on the first surface of the packaging substrate. A stiffener is disposed on the exterior of the at least one IC die. The stiffener has a first surface (160) disposed outside the sidewall of the package substrate and combined with the sidewall. The stiffener has a second surface (158, 358) bonded to at least one of the first and second surfaces (102, 104) of the package substrate.

Description

technical field [0001] Embodiments of the present application relate generally to chip package assemblies, and more particularly to chip package assemblies that include at least one integrated circuit (IC) die disposed on a package substrate and stiffeners that stiffen the package substrate without out-of-plane deformation. Background technique [0002] Electronic devices such as tablets, computers, copiers, digital cameras, smart phones, control systems, and ATMs often employ electronic components that utilize chip-package components for improved functionality and higher component density. Traditional chip packaging schemes typically utilize a packaging substrate, often combined with a through-silicon via (TSV) interposer, to enable multiple integrated circuit (IC) die to be mounted on a single packaging substrate. An IC die may include memory, logic, or other IC devices. [0003] For conventional chip packaging schemes, out-of-plane deformation of the package substrate c...

AI Technical Summary

Problems solved by technology

However, especially in larger chip package assemblies, the stiffeners themselves may bend or twist, or even delaminate from the package substrate, thus still allowing undesired warping and bowing to occur during manufacturing and / or use

This warping and bowing of the package substrate can lead to failure of solder connections or other damage to components and devices of the chip package assembly, which can adversely affect device performance and reliability

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