Memory access method and device

Abstract

The application discloses a memory access method and device, belonging to the technical field of computers. The method comprises the following steps: determining a memory bank group BG to which a first instruction belongs during the process of executing instructions included in an instruction execution queue, wherein the first instruction is a last instruction included in the instruction executionqueue to be executed; when different instructions belonging to the same BG as the first instruction are present in an instruction buffer queue, selecting one instruction from the different instructions in the BG as a second instruction, wherein the different instructions belong to the same BG as the first instruction; and adding the second instruction into the instruction execution queue and accessing all BGs in a memory system in a balanced manner according to the instruction execution queue. The different instructions in the instruction buffer queue belonging to the same BG as the first instruction are always prioritized to add in the instruction execution queue. Therefore, instructions belonging to all BGs in the instruction execution queue are made balanced. Accordingly, balanced access of all the BGs in the subsequent period is ensured.

Description

technical field [0001] The embodiments of the present invention relate to the technical field of computers, and in particular to a memory access method and device. Background technique [0002] In a computer system, processors such as a central processing unit (Central Processing Unit, CPU) and a graphics processing unit (Graphics Processing Unit, GPU) usually access a memory system through a memory controller (Memory Controller, MC). Specifically, the processor can send the command to be executed to the MC; after the MC receives the command, it can execute the command to access the memory system. Wherein, the memory system may be implemented by a fourth-generation double data rate synchronous dynamic random access memory (Double-Data-Rate Fourth Generation Synchronous Dynamic Random Access Memory, DDR4 SDRAM). [0003] Such as Figure 1A As shown, the DDR4 SDRAM includes a plurality of bank groups (Bank Group, BG), and each BG in the plurality of BG includes a plurality of...

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Problems solved by technology

However, this method is only applicable to the access mode in which the system address is continuously incremented. For the system address changing at a high level, or other irregular access modes, it cannot make the BGs to which the multiple commands continuously sent by the processor to the MC belong are different, thus also It is impossible to realize the balanced access of subsequent MCs to each BG

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