A ldpc decoder based on random bit stream update

A random bit and decoder technology, applied in the field of LDPC decoders, can solve the problems of insufficient optimization of variable node update module design, redundant resource and architecture design, slow convergence speed, etc., to improve the operating clock frequency and data. Throughput, less unit resource occupancy, and reduced wiring difficulty

Active Publication Date: 2021-04-02
GLORY WIRELESS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the current architecture based on random bitstream updates has problems such as slow convergence speed, redundant resource usage and architecture design, insufficient optimization of variable node update module design, and large decoding delay.

Method used

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  • A ldpc decoder based on random bit stream update
  • A ldpc decoder based on random bit stream update
  • A ldpc decoder based on random bit stream update

Examples

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Embodiment Construction

[0037] The present invention will be further described below in conjunction with the accompanying drawings.

[0038] figure 1 It is an embodiment of an LDPC decoder based on random bit stream update described in the present invention. Each box represents a unit, and each unit is composed of different implementation components. The bold arrows indicate the data flow interaction, and the numbers above the arrows indicate the width of the data flow.

[0039] figure 2 It is an implementation method of using asynchronous FIFO for the input buffer unit, with a total depth of 256, a width of 5 bits, and different input and output bit widths. The input enters 40 bits per clock, occupying 8 FIFO units in total. 5 bits represent a received channel symbol amplitude, that is, quantized into 5 bits. FIFO outputs 80 bits per clock. In this way, for the 672-length LDPC code defined in 802.11ad, the input buffer is completed in 84 clock cycles, and the output of a code block is complete...

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Abstract

The present invention relates to the technical field of digital communications, and in particular, to an LDPC decoder based on random bitstream update. The decoder comprises a decoding control unit, an input buffer unit, an information conversion unit, a variable node update unit, a check node update unit, a code word check unit, and a serial output unit. The LDPC decoder is based on the random calculation principle, a variable node unit structure and a check node unit structure are simple, and then the wiring difficulties are reduced. The variable node update structure is used for signal sharing, and the resources occupied by the unit are reduced. Different construction modes are adopted for variable nodes of different degrees, so that the resources of the decoder are less, and the decoding speed is faster. By adopting the decoding optimization strategy of "alternate parameters" and "re-decoding", the decoding performance can be improved. A connection line between two layers of nodes adopts a "half-flooding" technology, and the operation clock frequency and data throughput of the LDPC decoder are effectively improved. By adopting a ''double check'' technology, the decoding convergence speed is faster.

Description

technical field [0001] The invention belongs to the technical field of digital communication and relates to an LDPC decoder based on random bit stream update. Background technique [0002] When information is transmitted on a channel, especially a wireless channel, it will experience noise interference and fading, resulting in more errors in the information received at the receiving end. Error correction control coding is a technology that can effectively solve this kind of problem. Error correction control coding completes the coding operation by adding redundant check bits to the original information bit string according to certain rules at the sending end, and performs decoding through corresponding decoding means at the receiving end to reduce the bit error rate. [0003] Low Density Parity Check Code (LDPC) is a kind of error correction control code with excellent error correction performance. It was first proposed by Robert G. Gallager in 1962. LDPC constructs a che...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/11
CPCH03M13/1131
Inventor 吕启福李帅罗志刚
Owner GLORY WIRELESS CO LTD
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