20 results about "Stochastic computing" patented technology

A circuit includes a first two-state device, a second two-state device and a third two-state device, each two-state device having a first resistance in a first state and a second resistance in a second state. First control elements are configured to apply a first voltage to the first two-state device to stochastically place the first two-state device in either the first state or the second state. Second control elements are configured to apply a second voltage to the second two-state device to stochastically place the second two-state device in either the first state or the second state. Third control elements are configured to send respective currents through the first two-state device and the second two-state device so as to place the third two-state device in either the first state or the second state based on the state of the first two-state device and the state of the second two-state devices.

The invention discloses a safety protection method and device for an STR scene, equipment and a storage medium, and relates to the technical field of computer application, the method comprises the steps that after an AP and an SP receive a SUSPend command, keys and sensitive information in a memory are cleared, and meanwhile the Checksum value of program data in a DDR is randomly calculated and stored; and after the SP Resume and before the AP Resume, randomly calculating the Checksum value of the program data in the DDR again, and comparing the Checksum value with the stored Checksum value so as to determine the Resume or the Reboot. The program data comprises Code segment data, Data segment data and Bss segment data. The application can ensure that sensitive information is not leaked, ensure that the program is not tampered, and eliminate the possibility of being attacked by illegal persons.

This invention discloses a low-power convolutional neural network hardware acceleration method based on random computation. First, a convolutional neural network model is constructed and trained. Then, during the inference phase, the trained model is deployed to a hardware computing unit, and random computation is used to partially or completely replace the convolutional computations in the model. The random computation includes three stages: encoding, computation, and decoding. In the encoding stage, the input feature map is scaled, and the convolutional kernel is quantized. The gray values ​​of the convolutional kernel and each point in the input feature map are normalized into probability values, and an encoding sequence is generated for each probability value. In the computation stage, the two encoding sequences of the convolutional kernel and corresponding points in the input feature map are subjected to a traversal AND operation to generate an AND operation sequence. In the decoding stage, the AND operation sequence is decoded to obtain the computation result. Without significantly affecting model performance, this method reduces computational complexity and hardware resource consumption, making it suitable for scenarios with limited power consumption and resources.

This invention discloses a method for calculating the dynamic reliability of electromechanical systems based on inter-component interoperability, comprising: (1) constructing a hidden Markov model for system risk transmission and an inter-component risk state transmission matrix; (2) combining load effects to calculate inter-component interoperability and resistance coefficients, quantifying relevant parameters of the state transition matrix, and calculating the probability that the risk of a component will not escalate after risk transmission; (3) applying inter-component interoperability, determining the final state sequence of the system based on the idea of ​​stochastic computation, and calculating the dynamic reliability of the system. For complex electromechanical systems, the interoperability calculation method of this invention can make the system reliability calculation closer to the actual situation, and based on this, an improved maintenance strategy is proposed. Compared with the traditional maintenance strategy, the maintenance strategy considering inter-component interoperability proposed in this invention can maintain the system at a higher reliability and have a lower maintenance cost in the long term.

An aspect of the invention includes an optimization unit configured to perform optimization, by stochastic calculation, on a Hamiltonian of a quantum annealing model, which is an Ising model representing the optimization target in a state in which a transverse magnetic field is applied, in which the optimization unit performs the optimization by executing a series of formulas satisfying a state update condition, which is a condition related to an update of a spin state, until a predetermined end condition is satisfied, and the state update condition includes a first condition representing the spin state, a second condition representing a relationship between the spin states obtained at different times, a third condition representing a relationship between adjacent trotter layers, and a fourth condition including an amount representing an intensity of an interaction between the same or different spins existing in the same trotter layer, an amount representing a magnitude of energy of a spin itself, and an amount representing an intensity of an interaction between spins belonging to different trotter layers.

Embodiments relate to devices, circuits, and systems including s-bit generators constructed from memtransistors. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. The s-bit generator can be used to construct s-bit generator circuits that exploit the different sources of inherent stochasticity in 2D memtransistors (e.g., cycle-to-cycle fluctuations in the carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor, random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor, etc.) and combine it with an inverting amplifier and a programmable thresholding inverter to obtain s-bits. Additional embodiments relate to integration of s-bit generators with 2D memtransistor based logic gates such as AND, MUX, XOR, and OR gates to perform arithmetic operations such as addition, subtraction, multiplication, and / or sorting.

The present application relates to the technical field of data processing, in particular to a kind of spectrum radius feature extraction and Hamiltonity determination method for mixed graph structure.It includes the following steps: obtaining mixed graph data and constructing adjacency matrix, Laplacian matrix and unsigned Laplacian matrix;Three spectrum radii are extracted using power iteration acceleration algorithm, and a spectrum radius pyramid is constructed by multi-layer coarsening, forming a multi-scale spectrum feature vector;The feature vector is input into the classification model to output the Hamiltonity probability value;The confidence score is calculated by multiple random dropout, and it is dynamically decided whether to activate the accurate determination engine;Finally, the determination result is output.The present application combines multi-scale spectrum features and statistical features, uses graph neural networks to achieve high-precision probability prediction, and improves the reliability of boundary samples through confidence evaluation and cascade determination architecture, suitable for graph data analysis in the fields of communication networks and bioinformatics.

Disclosed herein a method for agile simulation of a stochastic computing image processing where the input operands are processed with the aid of a correlation-controlled contingency table (CT) construct without using actual stochastic bit-streams. The disclosed method utilizes contingency tables to perform (i) template matching, (ii) image compositing, and (iii) pattern detection. Results show that the proposed approach achieves similar computation accuracy to the traditional stochastic computing simulation while performing runtime- and memory-efficient computations.

The patent discloses a random number generator for random calculation, comprising: an excitation unit, a first random unit, a second random unit and a sensing unit, wherein under the excitation of the excitation unit, the first random unit transforms from a high resistance state to a low resistance state with a first probability; under the excitation of the excitation unit, the second random unit transforms from a high resistance state to a low resistance state with a second probability; the second random unit randomly outputs a first or second or third or fourth response current according to the combined relationship between the resistance states of the first and second random units; and the sensing unit is used for sensing the first or second or third or fourth response current randomly output by the second random unit and generating a random number 1 or 0 according to the sensing result.

The invention relates to the technical field of edge AI chips, in particular to a distributed random pulse chip control method for a resource-constrained network. Comprising a heterogeneous neural computing core which is composed of a random computing neural convolution feature extractor and a miniature binary calibration coprocessor and is configured in an edge AI chip. The statistical confidence coefficient of random pulse calculation is monitored in real time through the random pulse flow analyzer, when the confidence coefficient reaches a preset threshold value, an early decision termination mechanism is triggered, calculation of the random calculation neural convolution feature extractor is stopped in advance, and a calculation result is transferred to the miniature binary calibration coprocessor for decision calibration. According to the method, the inherent contradiction between the random calculation precision and the delay is effectively relieved, the energy efficiency ratio and the response speed of the edge AI chip are remarkably improved, and the service life of a battery of resource-limited network equipment is prolonged.

A cost-effective and highly efficient bit-stream generator for stochastic computing division circuits implementing powers-of-2 Van der Corput (VDC) sequences for bit-stream generation, providing high accuracy operation and low-cost implementation. The correlator design provides high-quality input bit-streams for all stochastic computing division designs, wherein a single random number generator is shared among the input bit-streams of the stochastic computing divider circuit.

The invention provides a mean value addition calculation device and method based on random calculation, and belongs to the field of integrated circuit design. The device comprises a random bit stream generation unit, a DD-MAX unit and a mean value addition units, the mean value addition unit comprises two AND gates and an OR gate, and the output ends of the two AND gates in the mean value addition unit are respectively connected with the two input ends of the OR gate; the division series n of the mean value addition unit is calculated, and X represents the number of binary numbers to be calculated; dividing the mean value addition unit into n levels of mean value addition units; the n levels of mean value addition units are called a first-level mean value addition unit, a second-level mean value addition unit,..., and an n-level mean value addition unit respectively. When the mean value addition calculation device is used for carrying out mean value addition calculation, the obtained MSE is low, and it is indicated that the mean value addition calculation device can have high calculation precision.

The invention discloses a transform reasoning accelerator based on random calculation. The transform reasoning accelerator comprises a random bit stream generation unit, a random calculation unit and a random calculation unit, wherein the random bit stream generation unit is used for generating a random bit stream which is in probability correspondence with an input fixed-point numerical value according to the input fixed-point numerical value; the random multiplication and addition operation unit is used for executing bitwise multiplication operation on the random bit stream from the random bit stream generation unit and accumulating bitwise multiplication output through a parallel counter in a preset sampling period to generate a multiplication and addition result of probability estimation; the nonlinear function approximation unit is used for executing polynomial approximation on the probability accumulation result from the bit-level multiply-add operation unit so as to generate nonlinear activation function output required in Transform; and the random bit stream generation unit is connected with the random multiplication and addition operation unit and the nonlinear function approximation unit to form a complete reasoning accelerator data path. The invention provides a random calculation Transform reasoning accelerator based on a sobol sequence. The random calculation Transform reasoning accelerator has the advantages of being low in power consumption, small in area and high in robustness.

The invention provides a large model acceleration system and method based on random calculation, a medium, a terminal and a program product, and the system comprises a random bit stream coding module which is used for coding a weight parameter and an input feature of a large model into a random bit stream with a preset bit number from a floating-point number; the random calculation acceleration module is used for carrying out multiply-add operation and activation function operation according to the weight parameters converted into the random bit streams and the input characteristics so as to obtain an operation result; and the random bit stream decoding module is used for decoding the operation result of the random bit stream into a floating-point number format. According to the method, on the premise of ensuring the reasoning and training precision of the large model, the hardware cost is reduced, the computing architecture is simplified, the energy efficiency ratio is improved, meanwhile, the mainstream large model is supported, and the universality and deployment flexibility are considered.

Disclosed herein is a finite state machine-based low-discrepancy bit-stream generator that support generation of any number of independent low-discrepancy bit-streams. Here, the order of bit selection by the FSM of the bit-stream generator is determined based on the distribution of numbers in the Sobol sequences. An independent LD bit-stream is generated by setting up the FSM using a different Sobol sequence. The available space can then be used to improve fault tolerance.

This invention discloses a gas identification method based on a lightweight convolutional neural network using memristor random computation. The method is characterized by: firstly, collecting 16 gas feature data points using 16 gas sensors, obtaining 16 bitstreams through a memristor array, and then performing convolution, pooling, and fully connected operations on these bitstreams using memristor random computation to obtain 6 bitstreams. These 6 bitstreams are used to define and represent 6 gas categories, and the final gas classification result is obtained by comparison. Its significant advantages are: using a convolutional neural network with shared weight parameters reduces the number of parameters in the model; employing random computation for hardware deployment accelerates network computation speed while resisting data drift; and utilizing the random switching characteristics of memristors to generate random bitstreams further reduces energy consumption.

A magnetic tunnel junction device includes a pinned magnetic layer, a free magnetic layer, and a tunnel barrier layer between the pinned and free magnetic layers. The free magnetic layer includes a first free layer, a second free layer spaced apart from the tunnel barrier layer with the first free layer therebetween, and a spacer layer between the first free layer and the second free layer. The first free layer and the second free layer are antiferromagnetically coupled to each other by the spacer layer, and each of the first free layer and the second free layer has a magnetization direction substantially perpendicular to an interface between the free magnetic layer and the tunnel barrier layer. A thermal stability of the free magnetic layer is in a range of 0 to 15.

A random source circuit for random computing and a configuration optimization method thereof, wherein the random source is generated by m linear feedback shift registers for m n-bit random binary numbers; the bits of the random binary numbers generated by the linear feedback shift registers are rearranged by m+1 n-bit rearrangement elements; the bits generated by the rearrangement elements are selected by 2m bit selection elements and combined to generate m new n-bit random binary numbers as the final random source output. The present application is optimized for any random computing circuit, and on the basis of maintaining high computing accuracy, the hardware overhead is greatly reduced, realizing high computing accuracy and low hardware overhead, achieving efficient random source design; no longer limited to random computing circuits for implementing single-variable functions, with wide application potential.