39 results about "Stochastic computing" patented technology

The invention relates to a random calculation processing unit and method based on a self-adaptive compensation mechanism, and the method employs a self-adaptive compensation core formed by solidifying a lightweight neural network to replace a conventional solidification compensation rule, and the self-adaptive compensation core can carry out the random calculation according to two operands participating in multiplication. And an optimal compensation parameter is dynamically predicted in real time for compensation. According to the scheme, the calculation error of random calculation is accurately, continuously and individually compensated in a data driving mode, and hardware implementation is performed by adopting a constant coefficient multiplier technology, so that the self-adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the method has the advantages that the fidelity of random calculation can be greatly improved on the premise that the hardware cost is not remarkably increased, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random calculation neural network accelerator.

The invention discloses a multi-scale power load prediction method and system, and the method comprises the steps: obtaining time series data related to power generation, and decomposing the time series data into a plurality of sub-series data, so as to capture key periodic features in the data; the time sequence data and the subsequences are sent into an encoder and a decoder for feature extraction, in the encoder, local important information is extracted through an expansion causal convolutional network, correlation features between the subsequences are fused into a subsequent attention module, in the encoder, an attention mechanism is sampled through a probabilistic fragment, and the time sequence data and the subsequences are extracted; randomly calculating the attention of a plurality of local blocks, performing dynamic pruning, capturing global dependency on coarse granularity through a multi-scale sparse attention mechanism, identifying a macroscopic mode of a sequence, and calculating a relationship between time steps on fine granularity to capture local dependency; and constructing and training a prediction model based on the encoder and the decoder, outputting a prediction result of the power load data, and performing result evaluation through dimensionality reduction and a loss function.

The invention discloses a numerical comparator which comprises a storage unit array, storage units of the storage unit array are connected through word lines and bit lines to form an array, and first numbers participating in comparison are sequentially stored in the storage units of different word lines on the same bit line according to a bit sequence. The different word lines on the same bit line form a first word line group, and a second number participating in comparison is sequentially stored in a memory unit of a word line, which is different from any word line in the first word line group, on the same complementary bit line corresponding to the bit line according to a bit sequence. The word lines different from any word line in the first word line group form a second word line group, and the bit lines and the complementary bit lines are connected to the input ends of the sensing amplifiers corresponding to the bit lines. And the memory unit is a DRAM (Dynamic Random Access Memory) unit storage unit. The first number and the second number are binary numbers.

A circuit includes a first two-state device, a second two-state device and a third two-state device, each two-state device having a first resistance in a first state and a second resistance in a second state. First control elements are configured to apply a first voltage to the first two-state device to stochastically place the first two-state device in either the first state or the second state. Second control elements are configured to apply a second voltage to the second two-state device to stochastically place the second two-state device in either the first state or the second state. Third control elements are configured to send respective currents through the first two-state device and the second two-state device so as to place the third two-state device in either the first state or the second state based on the state of the first two-state device and the state of the second two-state devices.

The invention discloses a safety protection method and device for an STR scene, equipment and a storage medium, and relates to the technical field of computer application, the method comprises the steps that after an AP and an SP receive a SUSPend command, keys and sensitive information in a memory are cleared, and meanwhile the Checksum value of program data in a DDR is randomly calculated and stored; and after the SP Resume and before the AP Resume, randomly calculating the Checksum value of the program data in the DDR again, and comparing the Checksum value with the stored Checksum value so as to determine the Resume or the Reboot. The program data comprises Code segment data, Data segment data and Bss segment data. The application can ensure that sensitive information is not leaked, ensure that the program is not tampered, and eliminate the possibility of being attacked by illegal persons.

This invention discloses a low-power convolutional neural network hardware acceleration method based on random computation. First, a convolutional neural network model is constructed and trained. Then, during the inference phase, the trained model is deployed to a hardware computing unit, and random computation is used to partially or completely replace the convolutional computations in the model. The random computation includes three stages: encoding, computation, and decoding. In the encoding stage, the input feature map is scaled, and the convolutional kernel is quantized. The gray values ​​of the convolutional kernel and each point in the input feature map are normalized into probability values, and an encoding sequence is generated for each probability value. In the computation stage, the two encoding sequences of the convolutional kernel and corresponding points in the input feature map are subjected to a traversal AND operation to generate an AND operation sequence. In the decoding stage, the AND operation sequence is decoded to obtain the computation result. Without significantly affecting model performance, this method reduces computational complexity and hardware resource consumption, making it suitable for scenarios with limited power consumption and resources.

This invention discloses a method for calculating the dynamic reliability of electromechanical systems based on inter-component interoperability, comprising: (1) constructing a hidden Markov model for system risk transmission and an inter-component risk state transmission matrix; (2) combining load effects to calculate inter-component interoperability and resistance coefficients, quantifying relevant parameters of the state transition matrix, and calculating the probability that the risk of a component will not escalate after risk transmission; (3) applying inter-component interoperability, determining the final state sequence of the system based on the idea of ​​stochastic computation, and calculating the dynamic reliability of the system. For complex electromechanical systems, the interoperability calculation method of this invention can make the system reliability calculation closer to the actual situation, and based on this, an improved maintenance strategy is proposed. Compared with the traditional maintenance strategy, the maintenance strategy considering inter-component interoperability proposed in this invention can maintain the system at a higher reliability and have a lower maintenance cost in the long term.

The present application provides a kind of vulnerability assessment and vulnerable node identification method for regional bridge and tunnel network security operation and maintenance.The method comprises the following steps:1, the basic information of regional bridge and tunnel is preprocessed and integrated, and regional bridge and tunnel network is established;2, based on graph theory and complex network theory analysis bridge and tunnel network characteristics, get the key node of bridge and tunnel network topology structure;3, comprehensive accessibility and network efficiency, select appropriate vulnerability index, take different node failure strategy, calculate the corresponding relationship of node removal ratio and vulnerability index;4, calculate the overall vulnerability of bridge and tunnel network, analyze the vulnerability of network and record the vulnerability of each bridge and tunnel node;5, using Monte Carlo sampling method, through multiple random calculation of the vulnerability of bridge and tunnel node, identify the vulnerable node of bridge and tunnel network.The present application is suitable for the topological analysis, vulnerability analysis and key vulnerable node identification process of general regional bridge and tunnel network.

An aspect of the invention includes an optimization unit configured to perform optimization, by stochastic calculation, on a Hamiltonian of a quantum annealing model, which is an Ising model representing the optimization target in a state in which a transverse magnetic field is applied, in which the optimization unit performs the optimization by executing a series of formulas satisfying a state update condition, which is a condition related to an update of a spin state, until a predetermined end condition is satisfied, and the state update condition includes a first condition representing the spin state, a second condition representing a relationship between the spin states obtained at different times, a third condition representing a relationship between adjacent trotter layers, and a fourth condition including an amount representing an intensity of an interaction between the same or different spins existing in the same trotter layer, an amount representing a magnitude of energy of a spin itself, and an amount representing an intensity of an interaction between spins belonging to different trotter layers.

Embodiments of the present application provide a complex instruction set verification method and device, electronic equipment and storage medium, the method comprising: obtaining a target excitation signal; determining random data corresponding to the target excitation signal according to the target excitation signal, wherein the random data at least includes input instruction data and input instruction that can be operated; determining a random calculation result corresponding to the random data according to the random data; determining a verification result corresponding to the target excitation signal according to the random calculation result and the preset output result, in the embodiments of the present application, the UVM verification methodology is used to construct a verification platform to verify the complex instruction set of the chip, which aims to verify the complex instruction set by using all input instruction data in the random complex instruction set calculation process, and to judge the correctness of the complex instruction set in the chip, thereby providing the verification efficiency of the instruction set in the chip and saving manpower and material resources.

Embodiments relate to devices, circuits, and systems including s-bit generators constructed from memtransistors. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel formed between its source and its drain. The s-bit generator can be used to construct s-bit generator circuits that exploit the different sources of inherent stochasticity in 2D memtransistors (e.g., cycle-to-cycle fluctuations in the carrier trapping and detrapping phenomena in a gate insulator of a 2D memtransistor, thermal conductance fluctuations in a defect-engineered and scaled 2D memtransistor, random telegraph signals (RTS) in a defect-engineered and scaled 2D memtransistor, etc.) and combine it with an inverting amplifier and a programmable thresholding inverter to obtain s-bits. Additional embodiments relate to integration of s-bit generators with 2D memtransistor based logic gates such as AND, MUX, XOR, and OR gates to perform arithmetic operations such as addition, subtraction, multiplication, and / or sorting.

The present invention provides a convolutional neural network accelerator for data processing, comprising: a data processing unit and an adder array unit; the data processing unit includes a first preset number of random processing array modules, each random processing array module is used to process first data to be processed based on the fast finite impulse response (FIR) algorithm and bilinear stochastic computing to obtain a first output result; the adder array unit is used to perform cumulative summation on the first output result to obtain a target convolution result. By processing the data to be processed based on the fast finite impulse response (FIR) algorithm and bilinear stochastic computing, since the fast finite impulse response (FIR) algorithm only includes simple multiplication and addition calculations, and bilinear stochastic computing has the advantages of low complexity and high fault tolerance, the combination of the two effectively reduces the complexity of convolution calculations in the neural network, thereby reducing the hardware consumption caused by convolution calculations and improving the hardware efficiency.

The present application relates to the technical field of data processing, in particular to a kind of spectrum radius feature extraction and Hamiltonity determination method for mixed graph structure.It includes the following steps: obtaining mixed graph data and constructing adjacency matrix, Laplacian matrix and unsigned Laplacian matrix;Three spectrum radii are extracted using power iteration acceleration algorithm, and a spectrum radius pyramid is constructed by multi-layer coarsening, forming a multi-scale spectrum feature vector;The feature vector is input into the classification model to output the Hamiltonity probability value;The confidence score is calculated by multiple random dropout, and it is dynamically decided whether to activate the accurate determination engine;Finally, the determination result is output.The present application combines multi-scale spectrum features and statistical features, uses graph neural networks to achieve high-precision probability prediction, and improves the reliability of boundary samples through confidence evaluation and cascade determination architecture, suitable for graph data analysis in the fields of communication networks and bioinformatics.

Disclosed herein a method for agile simulation of a stochastic computing image processing where the input operands are processed with the aid of a correlation-controlled contingency table (CT) construct without using actual stochastic bit-streams. The disclosed method utilizes contingency tables to perform (i) template matching, (ii) image compositing, and (iii) pattern detection. Results show that the proposed approach achieves similar computation accuracy to the traditional stochastic computing simulation while performing runtime- and memory-efficient computations.

Disclosed herein are systems and methods for stochastic computing in memory (SCIM). A SCIM system includes one or more stochastic number generators embedded in a memory array, a processor, and a memory. The memory receives a plurality of data slices. A first dot product is calculated for a first data slice in the plurality of data slices using a first set of operands. The first set of operands is received and stored in a binary representation. The first set of operands is converted into binary stochastic bitstreams using the one or more embedded stochastic number generators.

The application discloses a kind of based on random computing digital filter device, comprising: preprocessing unit, for pre-processing input data;Input cache unit, for pre-processing data is cached and with preset time interval sequentially output cached data;Serial shift register group, for the data input is serially shifted, cache and output the data after serial shift processing;Data conversion unit, for the multiple data of parallel input is converted into multiple random bit sequence and output;Random computing unit, for the multiple random bit sequence and the logic operation processing of multiple filter coefficients configured in advance, obtain and output random filtering result;Data recovery unit, for converting random filtering result into binary data and output;Output cache unit, for caching and output binary data.The digital filter device of the application has low hardware complexity, low hardware resource overhead, and can ensure the calculation accuracy when bit flipping occurs.

The patent discloses a random number generator for random calculation, comprising: an excitation unit, a first random unit, a second random unit and a sensing unit, wherein under the excitation of the excitation unit, the first random unit transforms from a high resistance state to a low resistance state with a first probability; under the excitation of the excitation unit, the second random unit transforms from a high resistance state to a low resistance state with a second probability; the second random unit randomly outputs a first or second or third or fourth response current according to the combined relationship between the resistance states of the first and second random units; and the sensing unit is used for sensing the first or second or third or fourth response current randomly output by the second random unit and generating a random number 1 or 0 according to the sensing result.

An efficient hardware design for a fuzzy noise reduction filtering in a stochastic computing system. The filtering device and method comprises two main stages: edge detection and fuzzy smoothing. The fuzzy difference, which is encoded as bit-streams, is used to detect edges. Then, fuzzy smoothing is done to average the pixel value based on eight directions. Experimental results show a significant reduction in the hardware area and power consumption compared to the conventional binary implementation while preserving the quality of the results.

The present application relates to a random computing processing unit and method based on an adaptive compensation mechanism, which replaces the traditional fixed compensation rule with an adaptive compensation core solidified by a lightweight neural network, and the adaptive compensation core can predict an optimal compensation parameter in real time and dynamically according to two operands participating in multiplication operation to perform compensation. Through the data-driven mode, the scheme realizes accurate, continuous and personalized compensation of the calculation error of random calculation, and through the constant coefficient multiplier technology, the adaptive compensation core has extremely low area and power consumption overhead in hardware. Compared with the prior art, the fidelity of random calculation can be greatly improved without significantly increasing the hardware cost, and a new effective way is provided for constructing a high-performance and high-energy-efficiency random computing neural network accelerator.

The present invention proposes a device and method for approximating arithmetic square roots based on random computation, belonging to the field of integrated circuit design. The device comprises a random sequence generation unit and a square root calculation unit; the random sequence generation unit includes a linear feedback shift register and a comparator; the square root calculation unit includes a square root settlement unit, an uncorrelated median generation unit, a half-value scaling unit, and a data coupling unit. The device for approximating arithmetic square roots based on random computation, described in the present application, achieves high computational accuracy when performing square root calculations on a 3- to 10-digit binary number X, with low average root mean square error and average mean absolute error.

A random number generator for accurate and energy-efficient stochastic computing, providing a low-cost and energy-efficient Low-discrepancy Sequence Generator derived from Powers-of-2 Van der Corput (VDC) sequences.

A random computation edge detection enhancement method, system, medium and equipment based on random resonance, in the method, an image is collected and taken as an input image, the input image is converted into a gray image, and a gray value matrix is obtained by normalizing the gray value; a pulse excitation is applied, a random bit stream is generated by random flipping of a memory, and each gray value in the gray value matrix is represented by using the random bit stream; random computation is performed on the random bit stream to obtain an edge detection result; a noise signal generated during the operation of an electronic device used for collecting the image is captured, and a random bit stream with a predetermined probability is generated by sampling; and the noise random bit stream with the predetermined probability is injected into the edge detection result to achieve enhancement and optimization.

Disclosed herein are three context-aware architectures to accelerate the three state-of-the-art deterministic methods of SC. The proposed designs employ a control unit to extract the minimum bit-width required to precisely represent each input data. The lengths of bit-streams are reduced to the minimum lengths required to precisely represent each input data. The noise-tolerance property of the designs is preserved as each bit-flip can only introduce a least significant bit error. The proposed designs achieve a considerable improvement in the processing time at a reasonable hardware cost overhead. The proposed designs make the deterministic bit-stream processing more appealing for applications that expect highly accurate computation and also for error-tolerant applications.

The present invention discloses a coarse-grained reconfigurable processor architecture based on stochastic computing. The reconfigurable processor architecture includes: a configuration memory for storing configuration information; a data memory for storing data; a central processor for performing computational processing on the data stored in the data memory; and a dynamically reconfigurable PE array for controlling data operations on the computational processing performed by the central processor by using a multiplier and an adder-shifter based on stochastic computing according to the configuration information stored in the configuration memory. The present invention applies stochastic computing to the design of the CGRA, dynamically changing the computing precision of the CGRA, so that computational tasks can be completed with lower power consumption in scenarios where the requirement for computing precision is not high, greatly improving the energy efficiency of the CGRA.

The invention relates to the technical field of edge AI chips, in particular to a distributed random pulse chip control method for a resource-constrained network. Comprising a heterogeneous neural computing core which is composed of a random computing neural convolution feature extractor and a miniature binary calibration coprocessor and is configured in an edge AI chip. The statistical confidence coefficient of random pulse calculation is monitored in real time through the random pulse flow analyzer, when the confidence coefficient reaches a preset threshold value, an early decision termination mechanism is triggered, calculation of the random calculation neural convolution feature extractor is stopped in advance, and a calculation result is transferred to the miniature binary calibration coprocessor for decision calibration. According to the method, the inherent contradiction between the random calculation precision and the delay is effectively relieved, the energy efficiency ratio and the response speed of the edge AI chip are remarkably improved, and the service life of a battery of resource-limited network equipment is prolonged.

A cost-effective and highly efficient bit-stream generator for stochastic computing division circuits implementing powers-of-2 Van der Corput (VDC) sequences for bit-stream generation, providing high accuracy operation and low-cost implementation. The correlator design provides high-quality input bit-streams for all stochastic computing division designs, wherein a single random number generator is shared among the input bit-streams of the stochastic computing divider circuit.

The present application relates to a training method, device, electronic device and medium of a convolutional neural network model, including: obtaining a pre-trained network model; respectively performing quantization processing and pruning processing on the pre-trained network model to obtain a target lightweight network model; designing a general deterministic stochastic computing convolutional module and a deterministic stochastic computing pooling module by means of high-level synthesis; and deploying the target lightweight network model on a field-programmable gate array according to the deterministic stochastic computing convolutional module and the deterministic stochastic computing pooling module. The present application realizes the combination of the convolutional neural network model and stochastic computing through a linear feedback shift register, and realizes the deployment of the convolutional neural network model in a field-programmable gate array through high-level synthesis, which can greatly improve the deployment efficiency of the convolutional neural network model and reduce the deployment cost of the convolutional neural network model.

The invention relates to a random calculation-based reconfigurable tap finite impulse response filter device, which supports a user to dynamically configure a tap starting state and a filtering weight, and realizes symbol-perceived bit stream coding through external random number driving. A dynamically reconstructed multi-stage MUX weighting path is combined, so that the filtering task requirements in which different taps participate are effectively met; and the integrator performs statistical estimation on the weighting result and outputs a filtering result. The whole process realizes closed-loop control through software and hardware cooperation and state management, has good flexibility and resource efficiency, and is suitable for a multi-mode low-power-consumption signal processing scene.