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Error-free adder based on random calculation

A random calculation and adder technology, applied in CAD circuit design and other directions, can solve problems such as inability to meet high-precision scenarios, uncontrollable calculation errors, and low accuracy of calculation units, saving resources and power consumption, reducing resources and power consumption. , easy to achieve effect

Active Publication Date: 2020-01-17
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, the traditional random adder used in this method is generally completed by an OR gate or a multiplexer, and the OR gate will all be "1" when "0" and "1" are added; The processor requires that the randomness of the selection sequence involved in the calculation is high enough, otherwise uncontrollable calculation errors will occur, which is very difficult to achieve
These computing units have low precision and cannot meet high-precision scenarios

Method used

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  • Error-free adder based on random calculation
  • Error-free adder based on random calculation
  • Error-free adder based on random calculation

Examples

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Embodiment Construction

[0028] The core of the present invention is that the adder designed based on the random calculation method can be error-free and infinitely cascaded, the positions of "0" and "1" in the input sequence can be arbitrary, and the FPGA implementation of the adder is given.

[0029] Below in conjunction with accompanying drawing, specifically illustrate the present invention:

[0030] The functional function of the two-input adder is z=x+y, where x and y represent input data, and z is the output of the adder. The input data binary bit width is k bit. A traditional random adder consists of, for example, figure 1 The OR gate shown in (a) or as figure 1 The multi-way gate shown in (b) realizes, wherein the random adder that realizes by OR gate requires that two-way input random sequence one road is centralized distribution, another way is uniform distribution; And the random addition that is realized by multi-way gate device contains uncertainty. Errors will occur in the calculati...

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Abstract

The invention discloses an error-free adder based on random calculation, which is applied to the field of digital circuit optimization design. Aimed at the error problem of an existing random adder, the error-free adder comprises an input converter, a random adder and an output converter. The input converter is used for converting input data into a random sequence, '0' and '1' in the random sequence of the input random adder can be at any position, the random adder is used for completing the additive operation of the random sequence, and the output of the random adder comprises an additive result and an error. The output converter is used for converting the addition result back to the traditional binary numerical domain through accumulation, and performing shift operation and accumulationon the error according to the cascade stage number of the error to compensate to obtain a final error-free result. The error-free adder disclosed by the invention has good universality.

Description

technical field [0001] The invention belongs to the field of optimal design of digital circuits, and relates to a method for realizing an error-free random calculation unit. Background technique [0002] With the development of information technology, the complexity of various signal processing algorithms is also increasing rapidly, and the traditional semiconductor technology is close to the physical limit. Moore himself believes that Moore's Law will be eclipsed by 2020. The optimization of integrated circuits mainly comes from the innovation of its design architecture, so it is necessary to study new algorithms to optimize the design of integrated circuits. [0003] Some scholars apply random computing to neural networks and digital signal processing. The main idea is to convert the traditional binary representation into a string of random sequences, where the ratio of "1" to the total length of the sequence represents the probability value. The calculation is done by th...

Claims

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Application Information

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IPC IPC(8): G06F30/34
Inventor 卢有亮王浩张恒源赵成卢鹏宇陈瑜滕云龙元硕成
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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