fc link elastic buffer circuit

Abstract

The present invention provides an FC link elastic buffer circuit, comprising: write data interface (1), IDLE detection circuit (2), write pointer control circuit (3), gray code conversion electrical port (4), IDLE flag memory circuit (5), data storage circuit (6), read-write pointer comparison circuit (7), current data is IDLE detection circuit (8), next data is IDLE detection circuit (9), read pointer plus 3 circuits (10), Read pointer control circuit (11), read data interface (12). The invention automatically detects the empty and full state of the receiving data buffer of the FC link through the hardware circuit, manages the continuous writing and elastic reading operation of the data at the receiving end of the FC port, and corrects the cumulative deviation of the clock frequency between the reading and writing clocks of the receiving buffer , to complete the precise matching of the data transmission rate of the sending and receiving ports, prevent data damage caused by overflow and underflow of the receiving buffer, ensure the integrity of the received data, and realize high-speed and highly reliable transmission of FC link data.

Description

technical field [0001] The invention belongs to the technical field of computers and particularly designs an elastic buffer circuit for FC links. Background technique [0002] With the development and application of FC technology becoming more and more mature, it becomes possible to use FC network as the backbone network in the airborne environment. FC node machines, FC switches and other equipment are widely used in the construction of FC network. Although all communication devices must work at the same frequency, due to the difference in clock phase and the process factors in the crystal oscillator manufacturing process, two clock frequencies are allowed. There are certain errors. [0003] The error of the clock specified by the FC network protocol is ±100×10 -6 , that is, a deviation of ±100 clock cycles is allowed in the time range of each million and ideal clock cycles. In the worst case, the maximum possible error of two different crystal oscillators is 200×10 -6 ,...

AI Technical Summary

Problems solved by technology

[0004] For the continuous data stream of high-speed transmission, the buffer used to buffer the received data, the write clock of the data comes from the clock of the sending end recovered from the received data, and the read clock comes from the clock generated by the local crystal oscillator of the receiving end. If it is not correct Dealing with the cumulative clock cycle skew between the write clock and the read clock will cause the overflow of the data receive buffer, corrupt the received data or cause data loss, seriously affecting the function and performance of system communication

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