Comparator offset voltage compensation circuit and method with fast, high-precision and variable step size

Abstract

The invention relates to a comparator offset voltage compensation circuit with fast, high-precision and variable step size, including a comparator, and its non-inverting input terminal V in+ They are respectively connected to the second end of the first switch S1 and the second end of the third switch S3, and the first end of the first switch S1 is connected to the non-inverting input signal V ip , the control terminal of the first switch S1 is connected to the second correction control signal, and the first terminal of the third switch S3 is connected to the common mode signal V cm , the control terminal of the third switch S3 is connected to the first correction control signal CAL; the inverting input terminal V of the comparator in‑ They are respectively connected to the second end of the second switch S2 and the second end of the fifth switch S5, and the first end of the second switch S2 is connected to the inverting input signal V in , the control terminal of the second switch S2 is connected to the second correction control signal. For a large range of offset voltage, first, coarse compensation is performed through a larger step size, so that the offset voltage is quickly reduced to a smaller range, and then the smaller range is used The step size enables high-precision correction, and finally realizes fast and high-precision correction of a wide range of comparator offset voltages.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a comparator offset voltage compensation circuit and method with fast, high-precision and variable step size. Background technique [0002] The comparator is a key module of the analog-to-digital converter, and its offset due to process mismatch will affect the performance of the analog-to-digital converter, especially for parallel structure ADCs, multi-bit SAR ADCs per step, and time-interleaved structure ADCs, etc. great influence. In order to reduce the offset voltage of the comparator, the traditional method is to use the input offset storage (IOS) and the output offset storage (OOS), both of which use two-phase non-overlapping clocks and storage capacitors to eliminate the offset, which will be in the input or output of the comparator The extra capacitance introduced at the terminal makes the speed of the comparator greatly slowed down. In addition, there...

AI Technical Summary

Problems solved by technology

In order to reduce the offset voltage of the comparator, the traditional method is to use the input offset storage (IOS) and the output offset storage (OOS), both of which use two-phase non-overlapping clocks and storage capacitors to eliminate the offset, which will be in the input or output of the comparator The introduction of additional capacitance at the terminal makes the speed of the comparator greatly slowed down

In addition, there is a method of adjusting the load capacitance of the output terminal, which can offset the offset of the comparator by adding a variable capacitor array or an adjustable capacitor, but this method will increase the load of the output terminal and reduce the speed of the comparator, and for a wide range Comparator offset voltage, in order to achieve high-precision correction, it is necessary to further increase the variable capacitor array or adjustable capacitors, which will increase the impact on the speed of the comparator

Another method is to add a compensation input MOS transistor at the input end, and adjust the input voltage of the compensation input transistor to offset the offset voltage of the comparator. However, the step size of the offset compensation in this method is fixed. To achieve high-precision correction, it is necessary to use a small The step size of , so that many calibration clock cycles are required to correct a wide range of offset voltages

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