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Method of variable bidirectional digital delay applied to radar simulation

A technology of analog data and radar, applied in the field of signal processing, can solve problems such as high design complexity and achieve high-resolution effects

Active Publication Date: 2018-10-16
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

In addition, the implementation of the double clock design using a single FIFO involves multiple control lines, resulting in high design complexity

Method used

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  • Method of variable bidirectional digital delay applied to radar simulation
  • Method of variable bidirectional digital delay applied to radar simulation
  • Method of variable bidirectional digital delay applied to radar simulation

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Embodiment Construction

[0031] 1. Set the synchronization signal of the signal, and the synchronization signal is synchronized with the signal.

[0032] 2. Set the read and write mode to read first and then write, such as Figure 4 ;

[0033] 3. The cycle counts to the size specified by the control word. After reaching the size specified by the control word, the pointer points to the 0 position. data0, data1, ... data (N-1) are the data written into the DRAM

[0034]

[0035] Output data when the delay is N:

[0036] The first shot: the input data overwrites the data at the original address 0, and the DRAM outputs the data 0 at the address 0, such as Figure 5 ;

[0037] The second shot: the input data overwrites the data of the original address 1, and the DRAM outputs the data 0 of the address 1, such as Image 6 ;

[0038] Nth shot: input data overwrites the data at the original address (N-1), and DRAM outputs data at the address (N-1) 0, such as Figure 7 ;

[0039] Beat (N+1): The point...

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Abstract

The invention discloses a method of variable bidirectional digital delay applied to radar simulation. The method belongs to signal processing technology, specifically relates to digital delay method.The method of variable bidirectional digital delay implementation based on a single port DRAM and a single clock provided by the invention has simple design structure. In the application of engineering, only needs to set control word, and loops count to the control word that a delay can be realized. Since a single working clock is adopted in the invention, the achievable operating frequency can reach the highest operating frequency of the FPGA. When the amount of delay is increased or decreased, only a value of increased or decreased of the amount of post-delay is required, which is a simple and efficient digital delay method with higher resolution.

Description

technical field [0001] The invention belongs to signal processing technology, and in particular relates to a digital delay method. Background technique [0002] Digital signal delay is widely used in digital signal processing, and has a very wide range of applications in radar, communication and other fields. [0003] There are two ways to delay digital signals through analog circuits and digital circuits. Generally speaking, the method of using traditional analog circuit technology to realize digital signal delay will be more complicated, the controllability is not good, and the integration level is not high. A typical method for implementing a digital circuit is to use a two-way digital delay based on a single FIFO and a double clock. This method uses twice the clock frequency to control the read and write enable signals of the FIFO. In FPGA technology, due to the limited clock frequency, if the read and write enable signal of the FIFO is controlled by twice the clock, t...

Claims

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Application Information

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IPC IPC(8): G11C11/4063
CPCG11C11/4063
Inventor 邹林姜帅龙王灿梁飞钱璐周云汪学刚
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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