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Integration of semiconductor structures

A semiconductor and subset technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., which can solve the problem of not simple stacking

Active Publication Date: 2018-10-23
INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

One possible method for integrating semiconductor structures with different chemistries is further disclosed as forming different alternating layer stacks comprising different first and second semiconductor materials in different regions on the substrate; however, in the substrate Forming such different stacks on the bottom is usually not simple

Method used

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  • Integration of semiconductor structures
  • Integration of semiconductor structures
  • Integration of semiconductor structures

Examples

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example 1

[0089] Example 1: According to one embodiment of the present invention, Si 1-x Ge x Nanowire conversion to Si 1-x’ Ge x’ Nanowires

[0090] we now refer to figure 1 . In the upper left corner, a surrounding layer of GeO is shown 2 (250) Si 1-x Ge x Cross-section of the nanowire (200). Heating Si 1-x Ge x nanowires (200), Si 1-x Ge x with Geo 2 A reaction between the Si 1-x Ge x Si atoms and GeO in 2 Ge atomic exchange in .

[0091] Depending on the environment, such as heating temperature and nanowire dimensions, this action may directly lead to (solid arrows), Si with a relatively uniform Ge concentration distribution 1-x’ Ge x’ nanowires (110), and a surrounding layer of Si 1-y Ge y o 2 (260), where y<1.

[0092] In other cases, the reaction may be confined to the outer shell (210) of the nanowire in the first step (dashed arrow), while the central part of the nanowire (220) may remain in contact with the initial Si 1-x Ge x Nanowires (200) are s...

example 2

[0098] Example 2: According to the present invention, Si 1-x Ge x Nanowire FET with Si 1-x’ Ge x’ Nanowire FET integration.

[0099] we now refer to Figure 4 a. Two semiconductor sub-devices are shown schematically in a cross-section taken perpendicular to the width of the fin structure and parallel to its longitudinal axis. Both semiconductor sub-devices typically exist on the same substrate (not shown). Each semiconductor sub-device includes a fin structure made of Si used to form nanowires 1-x Ge x (200, such as Si) and Si 1-z Ge z (100, z≤1, such as Si 0.7 Ge 0.3 ), dummy gates including dummy gate dielectrics (300) and dummy gate contacts (400), and sidewalls (500).

[0100] we now refer to Figure 4 b. An opening is made in alternating layers between two sidewalls (500) and inner sidewalls (610) are formed, then the opening is filled with a source or drain contact (700) and the source or drain contact is connected with a dielectric (700) cover (800)....

example 3

[0103]Example 3: According to the present invention, using dummy source / drain, Si 1-x Ge x Nanowire FET with Si 1-x’ Ge x’ Nanowires FET integration.

[0104] we now refer to Figure 5 a. Two semiconductor sub-devices are shown schematically, which are typically present on the same substrate. Each semiconductor sub-device includes a fin structure made of Si used to form nanowires 1-x Ge x (200, such as Si) and Si 1-z Ge z (100, eg Si 0.7 Ge 0.3 ), dummy gates including dummy gate dielectrics (300) and dummy gate contacts (400), and sidewalls (500).

[0105] we now refer to Figure 5 b. An opening is made in alternating layers between two sidewalls (500) and inner sidewalls (610) are formed, then the opening is filled with dummy source or drain contacts (710). Note that, contrary to the comparative example, the inner sidewall (610) is 1-z Ge zz The level of the layer (100) is fabricated for both sub-devices; thereby avoiding the problem of having to fabric...

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Abstract

In a first aspect, the present invention relates to a method for co-integrating Si 1-x Ge x structures (200) with Si 1-x' Ge x' structures (110) in a semiconductor device, comprising: a. providing a device comprising a plurality of Si 1-x Ge x structures (200), wherein 0 <= x < 1, b. depositing a layer of GeO 2 (250) on a subset of the Si 1-x Ge x structures (200), and c. heating at least the subset of Si 1-x Ge x structures (200) at a temperature high enough and for a time long enough to transform the subset of Si 1-x Ge x structures (200) into a subset of Si 1-x' Ge x' structures (110) withx'>x.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to the integration of semiconductor structures having different chemistries in such devices. Background technique [0002] In the fabrication of semiconductor devices, it may be useful to co-integrate semiconductor structures comprising different semiconductor materials, such as different channel materials. However, such co-integration is often difficult to achieve. For example, the first problem may be due to difficulties in the epitaxial growth of the first semiconductor material on a different semiconductor material. Another problem may also be the increased complexity of the device layout and its impact on several modules, eg separate inner sidewall modules may be required for different channel materials, and doing this is often not a simple matter. Another problem may also be vertical misalignment between different semiconductor materials, for example, in the case wher...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8232H01L29/26
CPCH01L21/8232H01L29/26H01L21/02664H01L21/823412H01L29/42392H01L29/775H01L29/78684H01L29/78696H01L29/0673H01L29/66545H01L29/66742H01L29/66772H01L29/78654B82Y10/00H01L29/66439H01L21/0259H01L21/02603H01L21/02532H01L21/2255H01L21/823431H01L27/0886H01L29/6653H01L29/66553H01L29/6681H01L29/7853
Inventor K·沃斯汀
Owner INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
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