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Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip

A physical layer chip, high-speed interface technology, applied in the field of high-speed parallel-to-serial conversion design, can solve the problems of complex circuits, internal noise differential signals prone to delay differences, etc.

Active Publication Date: 2018-11-02
SHENZHEN STATE MICROELECTRONICS CO LTD
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Problems solved by technology

[0003] The purpose of the present invention is to provide a parallel-to-serial conversion circuit and device applied to high-speed interface physical layer chips, aiming to solve the problems of complex circuits, easy generation of internal noise and delay in output differential signals in traditional technical solutions difference problem

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  • Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip

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[0017] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0018] see Figure 1 to Figure 5 , the embodiment of the present invention provides a parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip for converting parallel data into differential serial data. The parallel-to-serial conversion circuit includes: a phase-locked loop 10, a parallel data sampling unit 20. A data selection and distribution control unit 30 , a first serial register 40 , a second serial register 50 and a differential serial data generating unit 60 .

[0019] It is worth noting that if figure 1 As shown, the embodiment of the present invention...

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Abstract

The invention belongs to the technical field of high-speed parallel-serial conversion design, and provides a parallel-serial conversion circuit applied to a high-speed interface physical layer chip. The parallel-serial conversion circuit comprises a phase-locked loop, a parallel data sampling unit, a data selection and dispatch control unit, a first serial register, a second serial register and adifferential serial data generation unit. According to a first clock and a second clock, parallel data is sampled by the parallel data sampling unit to generate an odd number of paths of parallel dataand an even number of paths of parallel data, the odd number of paths of parallel data and the even number of paths of parallel data are converted into an odd number of paths of serial data and an even number of paths of serial data by using the data selection and dispatch control unit, the serial data is processed by the differential serial data generation unit, and differential serial data is finally output. A pure digital circuit design method is adopted, and through the design of odd and even paths of circuit structures, the use frequency of the inside of the chip can be reduced, and theIP reuse of the parallel-serial conversion circuit of a high-speed interface physical layer under different processes can be better achieved.

Description

technical field [0001] The invention belongs to the technical field of high-speed parallel-serial conversion design, and in particular relates to a parallel-serial conversion circuit and device applied to a high-speed interface physical layer chip. Background technique [0002] At present, high-speed interfaces are more and more widely used, and physical layer interfaces of many protocols (such as PCIe, USB, SATA, SRIO, etc.) are implemented by Serializer-Deserializer (SerDes) technology. However, the realization of the physical layer of the high-speed interface has always been a difficult problem in the design of the industry due to the need for digital and analog hybrid circuit design. Parallel-to-serial conversion circuit, as an important part of SerDes circuit design, is used to send serialized differential data. Its design will directly affect the performance of the SerDes sending port. Most of the existing parallel-to-serial conversion circuits are custom-designed by...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M9/00
CPCH03M9/00Y02D10/00
Inventor 邱钧华谢文刚吴志远高新军陈柳明
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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