Parallel-serial conversion circuit and device applied to high-speed interface physical layer chip
A physical layer chip, high-speed interface technology, applied in the field of high-speed parallel-to-serial conversion design, can solve the problems of complex circuits, internal noise differential signals prone to delay differences, etc.
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[0017] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
[0018] see Figure 1 to Figure 5 , the embodiment of the present invention provides a parallel-to-serial conversion circuit applied to a high-speed interface physical layer chip for converting parallel data into differential serial data. The parallel-to-serial conversion circuit includes: a phase-locked loop 10, a parallel data sampling unit 20. A data selection and distribution control unit 30 , a first serial register 40 , a second serial register 50 and a differential serial data generating unit 60 .
[0019] It is worth noting that if figure 1 As shown, the embodiment of the present invention...
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