Branch processing method and system

Abstract

The invention provides a branch processing method suitable for an electronic computer / microprocessor. The method is characterized in that a sequential instruction is provided according to an instruction address provided by a processor core, the instruction address is mapped by a BTB to provide a branch target instruction, one of the above two instructions is selected by a branch judgment generatedby the processor core to be executed by the processor core, and thus no branch loss exists. Branch prediction is not used, and the performance loss of the processor caused by a branch prediction error is excluded.

Description

technical field [0001] The present invention relates to the field of electronic computers and microprocessors. Background technique [0002] Control hazards, also known as branches, are a major cause of performance loss in processor pipelines. Current mainstream microprocessors use branch prediction to eliminate branch penalties. figure 1 It is an embodiment of the existing microprocessor processing conditional branching method. 101 is a branch target buffer (BranchTarget Buffer, BTB), 105 is an instruction cache, and 108 is a processor core. A typical BTB stores branch instruction addresses, corresponding branch target instruction addresses, and their branch predictions. The plurality of branch instruction addresses stored in the BTB 101 are compared with the instruction address 106 generated by 108 . If there is a match, a control signal 103 is output to control the selector 104 according to the branch prediction 102 stored in the matching BTB row. If the branch is pr...

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Problems solved by technology

[0003] But branch prediction has unavoidable prediction errors

If the branch decision (branch decision) generated by the processor core executing the branch instruction is not the same as the branch prediction, the processing results of each pipeline segment before the pipeline segment that generates the branch decision in the processor pipeline must be cleared, and an instruction selected from the branch decision must be cleared. Start re-execution, resulting in performance loss

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