Integer and half-integer frequency divider based on characteristic state feedback

A characteristic state and frequency divider technology, applied in counting chain pulse counters, pulse counters, electrical components, etc., can solve the problems of non-universal, complex circuit structure, incomplete frequency division coefficient, etc., and achieve simple design and strong versatility Effect

Active Publication Date: 2018-11-23
FUDAN UNIV
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Problems solved by technology

[0005] The object of the present invention is to provide a kind of integer and half-integer frequency divider based on characteristic state feedback, to solve above-mentioned known integer and half-integ

Method used

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  • Integer and half-integer frequency divider based on characteristic state feedback
  • Integer and half-integer frequency divider based on characteristic state feedback
  • Integer and half-integer frequency divider based on characteristic state feedback

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Embodiment approach

[0042] (1) Substituting M=5 into relational formula 1, n=3 can be obtained, that is, the sub-state bit width is 3 bits, and correspondingly select Q as the frequency division clock output CLK_DIV;

[0043] (2) Substituting M=5 and n=3 into relational formula 2, we can get:

[0044]

[0045] (3) When the duty ratio of the input clock to be divided is 50%, in order to realize equal duty ratio frequency, substituting D=50%, M=5 and n=3 into relational formula 3, we can get:

[0046]

[0047] (4) Therefore, K=3 and H=0 are desirable, where: K 0 =K 1 =K X =1,H 0 =H 1 =0; Correspondingly, Q=001, 110, 011 can be respectively selected for the level-type characteristic states. Therefore, the possible logic circuit of the level-type state decoder is as follows image 3 As shown; since the frequency division factor is H=0, the output (TRG) of the trigger decoder can be a fixed level, such as Figure 4 shown can be directly connected to logic "0".

[00...

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Abstract

The invention belongs to the technical field of frequency dividers of integrated circuits, and particularly provides an integer and half-integer frequency divider based on characteristic state feedback. The frequency divider comprises a clock phase inverter, an N-bit binary counter, an output clock selector and a feedback controller; and the feedback controller comprises a level type characteristic state decoder, a triggering type characteristic state decoder, a level type inverter and a triggering type inverter. According to the frequency divider, by feeding back characteristic states determined by a frequency division coefficient and conducting phase processing on an input clock, the binary counter is triggered at the edge designated by a to-be-divided clock, and the counting bit corresponding to the frequency division coefficient is selected and output to serve as a frequency division clock; and only an interface signal of the binary counter needs to be processed, the internal structure of the binary counter does not need to be changed, the advantages of being simple in design and high in universality are achieved, and not only can complete integer and semi-integer frequency division be achieved, but also the duty ratio of the frequency division clock can be adjusted by taking a 0.5 input clock cycle as the precision.

Description

technical field [0001] The invention belongs to the technical field of frequency dividers of integrated circuits, in particular to integer and half-integer frequency dividers based on characteristic state feedback. Background technique [0002] The frequency divider converts the frequency to f in The clock to be divided is reduced to a frequency of f according to a certain frequency division factor (M) out The frequency division clock, where f out =f in / M, as the input clock of the electronic system, so it has a wide range of applications in the circuit. At the same time, because many applications require the input clock to have a certain duty cycle, for example: circuit structures such as pipelines require the clock to have a 50% duty cycle to ensure that the circuit can work efficiently; wireless receivers use a duty cycle of 25% quadrature signal generator for improved performance. Therefore, the duty cycle is also an important indicator of the frequency divider, an...

Claims

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Application Information

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IPC IPC(8): H03K23/66H03K23/68
CPCH03K23/66H03K23/68
Inventor 程旭曾晓洋
Owner FUDAN UNIV
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