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Phase calibration method and related phase-locked loop circuit

A phase-locked loop and phase calibration technology, which is applied to the automatic control of electrical components and power, can solve problems such as deviation and reduce the calibration speed of the phase-locked loop circuit 10

Inactive Publication Date: 2018-11-23
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when used to generate the predicted phase error Φ ES When the known data length of is insufficient, the predicted phase error Φ ES may deviate from the true phase error, reducing the calibration speed of the PLL circuit 10

Method used

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  • Phase calibration method and related phase-locked loop circuit
  • Phase calibration method and related phase-locked loop circuit

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Embodiment Construction

[0045] Please refer to figure 2 , figure 2 It is a schematic diagram of a phase-locked loop circuit 20 in an embodiment of the present invention. The PLL circuit 20 is used to calibrate an input signal IN and a reference signal (not shown in figure 2 ) between phase errors. Such as figure 2 The PLL circuit 20 shown includes a multiplier 200 , a phase error detection unit 202 , a filter 204 , an oscillator 206 , a phase error prediction module 208 and a phase error adjustment module 210 . It is worth noting that, since the multiplier 200, the phase error detection unit 202, the filter 204, and the oscillator 206 in the phase-locked loop circuit 20 operate in the same manner as the multiplier 100, the phase error detection unit 102, the filter The device 104 and the oscillator 106 are the same, and the description is omitted here for the sake of brevity.

[0046] It is worth noting that the phase error prediction module 208 calculates the header phase error Φ of the kno...

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Abstract

The invention discloses a method for processing phase calibration. The method is used for a phase locked-loop circuit in a wireless communication device, and comprises the following steps: computing aheader phase error of a header sub-frame of one frame in an input signal and a guiding phase error of a guiding sub-frame in the frame, wherein the header sub-frame and the guiding sub-frame are known data; generating a prediction phase error according to the relation between the header phase error and the guiding phase error; generating a phase compensation signal according to the prediction phase error and a filter signal; adjusting the input signal according to the phase compensation signal so as to generate a compensation input signal; detecting a phase error between one guiding data sub-frame corresponding to the guiding sub-frame in the compensation signal and a reference signal; and generating the filter signal according to the phase error.

Description

technical field [0001] The present invention refers to a phase calibration method and a related phase-locked loop circuit, especially a phase calibration that can predict the phase error of the unknown data in the input signal based on the relationship between the phase errors calculated by the known data in the input signal Method and related phase-locked loop circuit. Background technique [0002] A Phase Locked-Loop (PLL) circuit is used to generate a periodic output signal, and the periodic output signal is expected to have a fixed phase relationship with a periodic input signal. Phase-locked loop circuits are widely used in various circuit systems, such as data and clock recovery circuits (Clock and DataRecovery), transceiver modules (Transceiver) or clock generators (Frequency Synthesizer) in wireless communication systems, and Not limited to this. [0003] Please refer to figure 1 , figure 1 It is a schematic diagram of a PLL circuit 10 in the prior art. The PLL ...

Claims

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Application Information

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IPC IPC(8): H03L7/08H03L7/085
CPCH03L7/0805H03L7/085
Inventor 卓庭楠郑凯文童泰来
Owner MEDIATEK INC