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Computer chip and operating method thereof

A computing chip and computing node technology, applied in computing, computers, digital computer components, etc., can solve problems such as limiting computing efficiency

Active Publication Date: 2019-01-01
SHENZHEN MICROBT ELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the hardware resources used for computing or storage usually adopt a centralized design architecture, the use or access of multiple core resources of the computing chip will be competitive, which greatly limits the efficiency of computing

Method used

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  • Computer chip and operating method thereof
  • Computer chip and operating method thereof
  • Computer chip and operating method thereof

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Embodiment Construction

[0018] figure 1 An existing computing chip 10 is illustrated. Such as figure 1 As shown, multiple CPUs (Central Processing Units) 12 are connected to the same bus 14 and exchange data with each other through the bus 14 . Multiple CPUs 12 may also be connected to memory 16 via bus 14 and access data in memory 16 . Since the data interaction between multiple CPUs 12 and between the CPU 12 and the memory 16 needs to be completed through the bus 14, multiple data interaction requirements may occur at the same time, and this will affect the occupation authority of the bus 14 and the access authority of the memory 16. Creates competing demands, reducing the efficiency of parallel computing architectures. In addition, once the memory 16 fails, the entire computing chip 10 cannot continue to operate.

[0019] In this regard, the inventors of the present application hope to propose a computing chip with a new architecture and its operation method to achieve higher computing efficie...

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Abstract

The present disclosure relates to a computing chip and a method of operating the same. A computer chip is provided, include multiple compute nodes, Each compute node includes: a control circuit for controlling an operation of the computing node, an arithmetic circuit connected to the control circuit, the arithmetic circuit receiving data from the control circuit and performing arithmetic based onthe data, a memory connected to the control circuit and directly accessible by the control circuit, the memory including a plurality of storage areas; A routing circuit connected to the control circuit and connected to a routing circuit of an adjacent computing node, the routing circuit being capable of data interaction with the control circuit and capable of data interaction with a routing circuit of an adjacent computing node.

Description

technical field [0001] The present disclosure relates generally to the field of integrated circuits and, in particular, to computing chips and methods of operating the same. Background technique [0002] With the increase of computing demand, people put forward higher and higher requirements for the computing power of hardware, and parallel computing also emerges as the times require. In order to realize parallel computing, existing computing chips often adopt the internal architecture of multi-core interconnection. However, since the hardware resources used for computing or storage usually adopt a centralized design architecture, the use or access of multiple core resources of the computing chip will be competitive, which greatly limits the efficiency of computing. [0003] Accordingly, there is a need for computing chips with novel architectures and methods of operation thereof. Contents of the invention [0004] An object of the present disclosure is to provide a nove...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/173G06F9/50
CPCG06F9/5027G06F15/17337
Inventor 范志军王欣杨作兴孔维新田文博李楠
Owner SHENZHEN MICROBT ELECTRONICS TECH CO LTD