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FPGA chip description file generation method, device, storage medium and electronic device

A technology for describing files and chips, applied in the field of FPGA, can solve the problems of multiple storage space, large amount of data, occupation, etc., and achieve the effect of reducing storage space

Inactive Publication Date: 2019-01-04
SHANGHAI FUDAN MICROELECTRONICS GROUP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In the prior art, the xdlrc file describes each tile and each primitive in detail, resulting in a large amount of data in the xdlrc file and taking up more storage space

Method used

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  • FPGA chip description file generation method, device, storage medium and electronic device
  • FPGA chip description file generation method, device, storage medium and electronic device

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Embodiment Construction

[0022] In the prior art, when describing all the tiles and primitives in the FPGA chip through the xdlrc file, each tile and each primitive is described in detail by means of flattening. Although the FPGA chip is fully described, there are many redundancy in the description file, resulting in a large amount of data in the file. Taking a Xilinx chip as an example, the description file size is 3.2G bytes.

[0023] In the embodiment of the present invention, when the tile information is described hierarchically, only the wire index, pip index, and site index in the tile information can be stored, without storing the specific connection relationship in the tile information, thus The storage space occupied by the FPGA chip description file can be reduced.

[0024] In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the ac...

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PUM

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Abstract

The invention relates to a method for generating FPGA chip description file, a device, a storage medium and an electronic device. The method comprises the following steps of: reading information of aprimitive device and information of a tile; the information of the primitive device comprises: a name, a number, a type of the primitive device, a pin set corresponding to the primitive device, an element set corresponding to the primitive device, and connection information corresponding to the primitive device. The tiles' information includes: the location of the tiles in the FPGA chip, the nameof the tiles, the type of the tiles and the connection resources of the tiles. The connection resources of the tiles include wire resources, pip resources and site resources. A description file of theFPGA chip is generated according to the information of the read primitive device and the information of the tile. The scheme can reduce the storage space occupied by the FPGA chip description file.

Description

technical field [0001] The present invention relates to the field of FPGA technology, in particular to a generation method, device, storage medium and electronic equipment of an FPGA chip description file. Background technique [0002] A field programmable gate array (Field Programmable Gate Array, FPGA) chip is a programmable device. A typical FPGA chip usually includes three types of basic resources: programmable logic function modules, programmable input / output modules, and programmable interconnect resources. . Programmable logic function module is the basic unit to realize user functions, usually regularly arranged into an array structure, distributed in the whole FPGA chip. The programmable input / output module is an interface connecting the internal logic of the chip and the external pins, surrounding the programmable logic function module. Programmable interconnection resources include connection line segments of various lengths and some programmable connection swit...

Claims

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Application Information

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IPC IPC(8): G06F17/22G06F17/50
CPCG06F40/14G06F30/34
Inventor 祁玉李佐渭李小南张青青
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP