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A method, system and terminal for avoiding clock looping in a digital synchronous network

A technology of clock looping and synchronous network, applied in the direction of time division multiplexing system, electrical components, multiplexing communication, etc., can solve the problems that affect the correct learning of MAC address

Active Publication Date: 2020-11-24
RAISECOM TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] 2) It can only communicate with devices using the same scheme
[0014] 1) Because the MAC address of the network element is placed in the position of the source MAC address of the ESMC message, the source MAC address in the message is modified, so it will affect the correct learning of the MAC address
[0015] 2) It can only communicate with devices using the same scheme

Method used

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  • A method, system and terminal for avoiding clock looping in a digital synchronous network
  • A method, system and terminal for avoiding clock looping in a digital synchronous network
  • A method, system and terminal for avoiding clock looping in a digital synchronous network

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Embodiment Construction

[0118] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0119] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0120] For network elements in a digital synchronous network, the types of clock sources include:

[0121] The internal clock source refers to the local crystal oscillator;

[0122] The external clock source refers to the clock source provided by other d...

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Abstract

The present invention discloses a method and a system for avoiding digital synchronization network clock ring formation and a terminal. The method comprises the steps of: receiving a clock identifierwith a clock source ID type sent by an adjacent network element or a clock identifier with an MAC address type having a corresponding relation with the clock source ID from a corresponding circuit through each circuit clock source; for each circuit clock source, determining whether the circuit clock source is available or not according to the received clock identifier; according to the received clock identifier type, determining the clock source ID transmitted by the adjacent network element, comparing whether the clock source ID is consistent with all the clock source IDs or not to determinewhether the circuit clock sources are available or not; selecting one clock source from the available clock sources as a current used clock source; and controlling each circuit clock source to send the clock identifier, the clock quality grade and the clock of the current used clock source to the adjacent network element through the corresponding circuit. The method and the system for avoiding digital synchronization network clock ring formation and the terminal can flexibly avoid clock ring formation.

Description

technical field [0001] The invention relates to clock synchronization technology, in particular to a method, system and terminal for avoiding clock looping in a digital synchronization network. Background technique [0002] Digital synchronous network technology is widely used. If there is a frequency difference and excessive drift between network elements in a digital synchronous network, frame slip and code slip will occur. In order to ensure reliable data transmission, frequency synchronization between network elements is required on the digital synchronous network to avoid data errors. [0003] In order to ensure the accurate synchronization of the frequency of each network element in the digital synchronization network, it is necessary for all network elements to obtain synchronous reference clocks from at least two paths. When the main link is disconnected, the entire network can switch to the backup link for protection. effect. The timing reference of the digital sy...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06H04J3/16
CPCH04J3/0602H04J3/0638H04J3/1611
Inventor 邱喜红
Owner RAISECOM TECH