A method, system and terminal for avoiding clock looping in a digital synchronous network
A technology of clock looping and synchronous network, applied in the direction of time division multiplexing system, electrical components, multiplexing communication, etc., can solve the problems that affect the correct learning of MAC address
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[0118] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.
[0119] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.
[0120] For network elements in a digital synchronous network, the types of clock sources include:
[0121] The internal clock source refers to the local crystal oscillator;
[0122] The external clock source refers to the clock source provided by other d...
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