Power flattening standard integrated circuit

Abstract

The invention relates to the field of information security and power attack resistance. In order to realize that a secure circuit does not leak internal information on a power supply to allow an attacker to fail in acquiring a key through a DPA (Differential Power Analysis) attack and in order to lower the risk that a discharge signal is attacked and improve the protective performance of a unit due to the use of a self-timed discharge method, the invention adopts a technical solution of a power flattening standard integrated circuit. The power flattening standard integrated circuit is composedof logic units connected in series with one another in sequence; the basic structures of the logic units are dual-rail dynamic logics; A, a symbol (as shown in the specification), B and a symbol (asshown in the specification) are input signals of the logic; CLK and a symbol (as shown in the specification) are clock control signals of the logic unit; and XOR is an output signal of the logic unit.The power flattening standard integrated circuit is mainly applied to the field of information security and an anti-power attack occasion.

Description

technical field [0001] The invention relates to the field of information security and the field of anti-power consumption attack. Specifically, it relates to power consumption flattening of standard integrated circuit cells. Background technique [0002] In today's society, cryptographic devices represented by smart cards (Smart Cards) and USB keys (USB Keys) are widely used in important fields such as telecommunications, finance, and pay TV, and have become key components of these applications. Therefore, their security is crucial important. Although the embeddedness of cryptographic devices makes it impossible for attackers to directly obtain the key information in cryptographic chips, since most cryptographic chips are composed of CMOS circuits, in this type of circuits, certain functions will be leaked when the circuits are working. The attacker uses differential power analysis (DPA) technology to analyze the correlation between key data and power consumption informati...

AI Technical Summary

Problems solved by technology

However, due to the use of a complex three-phase clock, the requirements for the clock signal and the difficulty of layout and wiring are increased, and the attacker can also attack the discharge signal of the unit, so that the TDPL unit has the risk of protection failure.

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