Three-Phase Single-Rail Precharge Logic Device

Abstract

The invention relates to the field of information security and the field of anti-power consumption attack, and aims to prevent an attacker from obtaining the difference in power consumption in the discharge stage by slowing down the clock, thereby making the protection invalid. At the same time, this kind of logic unit can make the power consumption of the unit the same in each evaluation cycle, eliminate the difference in power consumption under different input signals, and prevent the attacker from obtaining the key through the DPA attack. For this reason, the technical solution adopted by the present invention is that the three-phase single-rail precharge logic device includes a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4 and an NMOS transistor C1 for charge storage. The invention is mainly applied to the design and manufacture of integrated circuits.

Description

technical field [0001] The invention relates to the field of information security and the field of anti-power attack. Specifically, it relates to a three-phase single-rail precharge logic device. Background technique [0002] In today's society, cryptographic devices represented by Smart Cards and USB Keys are widely used in important fields such as telecommunications, finance, and pay TV, and have become key components of these applications. Therefore, their security is critical. important. Although the embeddedness of the cryptographic device makes it impossible for attackers to directly obtain the key information in the cryptographic chip, since most cryptographic chips are composed of CMOS circuits, in this type of circuit, the circuit will leak a certain amount of power during operation. The attacker uses the Differential Power Analysis (DPA) technology to analyze the correlation between the key data and the power consumption information, and analyzes the key by mathe...

AI Technical Summary

Problems solved by technology

Although in each evaluation cycle, the internal nodes of the logic unit will undergo one charge and discharge operation, but due to the difference in input signals, the internal nodes will perform two discharge operations in the evaluation phase and discharge phase respectively, so when the clock is After slowing down, the difference in discharge under different inputs will be detected, so TSPL has the risk of protection failure

Images