NMOS transistor and manufacturing method thereof

Abstract

The invention discloses an NMOS transistor. A manufacturing method of the NMOS transistor comprises the following steps: a P well is formed on the surface of a silicon substrate; a gate structure is formed on the surface of the P well; grooves are formed in the two sides of the gate structure; embedded epitaxial layers are arranged in the grooves; the embedded epitaxial layers include a silicon seed layer, a silicon-phosphorus body layer, a dual barrier layer located between the silicon-phosphorus body layer and the silicon seed layer, and a silicon cap layer protruding to the tops of the grooves; the dual barrier layer is formed by superposing a first barrier layer and a second barrier layer which are different in material; the silicon-phosphorus body layer has a phosphorus-heavily-dopedstructure; and the dual barrier layer is used for reducing the number of phosphorus of the embedded epitaxial layers, externally extending into the P well on the circumferential side, so as to reduceand prevent the influence of the externally-expanded phosphorus on a channel. The invention further discloses the manufacturing method of the NMOS transistor. The short channel effect of a device canbe improved, so that the stability of the device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an NMOS tube; the invention also relates to a manufacturing method of the NMOS tube. Background technique [0002] HKMG has a gate dielectric layer with a high dielectric constant (HK) and a metal gate (MG), so it is usually abbreviated as HKMG in the art. In MOS transistors using HKMG, the source and drain regions of NMOS often use embedded epitaxial layers. The material of the embedded epitaxial layers of NMOS is usually SiP. The stress of the channel region of NMOS is changed by the embedded epitaxial layer and the formation is beneficial. The tensile stress that improves the mobility of electrons in the channel region of the NMOS can improve the mobility of electrons in the channel region of the NMOS and reduce the channel resistance. [0003] With the development of technology, the critical dimension (CD) of the device is getting smaller and sma...

AI Technical Summary

Problems solved by technology

[0003] With the development of technology, the critical dimension (CD) of the device is getting smaller and smaller. For example, the technology node of the existing HKMG process, that is, the CD has reached below 28nm, which makes the short channel effect of the device more and more serious. , so that the performance of the device such as the stability of the device is seriously affected

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