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NMOS (N-channel Metal Oxide Semiconductor) tube and manufacturing method thereof

A manufacturing method and dummy gate technology, applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve problems such as the influence of device performance stability

Inactive Publication Date: 2019-03-15
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] With the development of technology, the critical dimension (CD) of the device is getting smaller and smaller. For example, the technology node of the existing HKMG process, that is, the CD has reached below 28nm, which makes the short channel effect of the device more and more serious. , so that the performance of the device such as the stability of the device is seriously affected

Method used

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  • NMOS (N-channel Metal Oxide Semiconductor) tube and manufacturing method thereof

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Embodiment Construction

[0045] The manufacturing method of the existing NMOS tube:

[0046] Before introducing the embodiment of the present invention in detail, introduce the manufacturing method of the existing NMOS tube, such as Figure 1A to Figure 1B Shown is a device structure diagram in each step of the manufacturing method of the existing NMOS tube; the manufacturing method of the existing NMOS tube includes the following steps:

[0047] Step one, such as Figure 1A As shown, a silicon substrate with a P well 101 formed on its surface is provided, a dummy gate structure is formed on the surface of the P well 101 , and a channel 103 is formed on the surface of the P well 101 covered by the dummy gate structure.

[0048] The dummy gate structure includes a first gate dielectric layer and a polysilicon dummy gate 102 formed on the surface of the P well 101 .

[0049] Silicon nitride spacers are formed on both sides of the dummy gate structure.

[0050] Step two, such as Figure 1A As shown, ...

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Abstract

The invention discloses an NMOS (N-channel Metal Oxide Semiconductor) tube which comprises a P trap formed on the surface of a silicon substrate, a gate structure formed on the surface of the P trap,grooves formed on the two sides of the gate structure, and embedded epitaxial layers formed in the grooves, wherein the embedded epitaxial layers comprise silicon seed layers, silicon-phosphorus bodylayers, barrier layers located between the silicon-phosphorus body layers and the silicon seed layers, and silicon cap layers extruding out of the tops of the grooves; the silicon-phosphorus body layers are in heavy phosphorus doping structures; the barrier layers are used for reducing the quantity of external expansion of phosphorus on the embedded epitaxial layers into the P trap on the peripheral side; and an influence of the externally expanded phosphorus on channels can be further reduced and prevented. The invention further discloses a manufacturing method of the NMOS tube. According tothe NMOS tube and the manufacturing method, a short channel effect of the device can be improved; and the stability of the device can be further improved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an NMOS tube; the invention also relates to a manufacturing method of the NMOS tube. Background technique [0002] HKMG has a gate dielectric layer with a high dielectric constant (HK) and a metal gate (MG), so it is usually abbreviated as HKMG in the art. In MOS transistors using HKMG, the source and drain regions of NMOS often use embedded epitaxial layers. The material of the embedded epitaxial layers of NMOS is usually SiP. The stress of the channel region of NMOS is changed by the embedded epitaxial layer and the formation is beneficial. The tensile stress that improves the mobility of electrons in the channel region of the NMOS can improve the mobility of electrons in the channel region of the NMOS and reduce the channel resistance. [0003] With the development of technology, the critical dimension (CD) of the device is getting smaller and sma...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/06H01L27/092H01L21/336
CPCH01L27/092H01L29/0642H01L29/0684H01L29/66545H01L29/66553H01L29/78
Inventor 陈品翰
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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