Memory access method for a high-speed bus communication controller
A technology of memory access and bus communication, which is applied in the direction of instruments, data conversion, and electrical digital data processing, etc., can solve the problems of large communication delay and low access efficiency, and achieve the effect of reducing communication delay and improving access efficiency
Active Publication Date: 2019-03-26
TIANJIN JINHANG COMP TECH RES INST
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[0005] The invention proposes a memory access method for a high-speed bus communication controller to solve the technical problems of low access efficiency and large communication delay when the high-speed communication controller and a processor access the memory at the same time
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[0019] In order to make the purpose, content and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.
[0020] This embodiment proposes a memory access method for a high-speed bus communication controller, the principle of which is as follows figure 1 shown. The system used in the method is mainly composed of a processor interface module, a bus communication controller interface module, a FIFO and a memory interface control module. Wherein, the processing interface module and the bus communication controller interface module send memory read or write memory requests to the memory interface control module as required. The memory interface control module performs the operation of reading memory or writing memory according to the type of requested operation.
[0021] The memory access method for the high-speed bus communic...
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The invention belongs to the technical field of high-speed bus communication, and particularly relates to a memory access method for a high-speed bus communication controller. According to the memoryaccess method, a memory interface control module is used, and a cyclic priority mode is adopted to respond to read memory or write memory operation requests of a processor interface module and a bus communication controller interface module. By utilizing the memory access method provided by the invention, no fixed time slot requirement exists, the access bandwidth of the memory can be fully utilized, the communication request of a high-speed bus can be responded in real time, and the communication delay is reduced; And one-time operation supports reading and writing of 16M data to the maximumextent, so that the access efficiency of the memory is improved.
Description
technical field [0001] The invention belongs to the technical field of high-speed bus communication, and in particular relates to a memory access method for a high-speed bus communication controller. Background technique [0002] With the application of more and more high-speed bus communication protocols, it is inevitable for high-speed bus communication controllers to use large-capacity memory to cache communication data. Large-capacity data memory is generally realized by DDR SDRAM. The bus communication controller reads the data to be sent in the DDR and sends it to the bus according to the communication protocol. The data received by the bus communication controller from the bus is written into the DDR after being analyzed according to the communication protocol. The processor reads the data received in the DDR and writes the data to be sent into the DDR. In the process of high-speed bus communication, the processor and the bus communication controller often need to a...
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IPC IPC(8): G06F13/16G06F5/06
CPCG06F5/06G06F13/1668
Inventor 秦刚刚
Owner TIANJIN JINHANG COMP TECH RES INST