Semiconductor device and manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The method includes: providing a semiconductor preparation having a source region and a drain region; and sequentially stacking at least two gold half-units on the exposed surface of the source region and / or the drain region, and each gold half-unit is along a direction away from the semiconductor preparation It includes a semiconductor layer and a metal layer in turn, wherein the material of each semiconductor layer is independently selected from GeSi, Si or Ge, among the plurality of gold half-units, the gold half-unit with the smallest distance from the semiconductor preparation is the first gold half-unit, The first gold half-unit includes a first semiconductor layer and a first metal layer, and the work function of the metal of the first metal layer is smaller than that of other metal layers; heat treatment is carried out to the semiconductor preparation provided with a plurality of gold half-units, so that At least part of the material of the semiconductor layer reacts with part of the material of the adjacent metal layer to form at least three metal-semiconductor compound layers. The resistance of the semiconductor device manufactured by the manufacturing method is small.

Description

technical field [0001] The present application relates to the field of semiconductors, and in particular, to a semiconductor device and a manufacturing method thereof. Background technique [0002] As the CMOS technology generation enters the technology node of 16 / 14nm and below, the contact resistance of the source and drain regions plays a vital role in the improvement of device performance. Traditional CMOS devices usually only use one kind of metal silicide, and it is difficult to make N / P MOS form low contact resistivity at the same time. Moreover, due to the solid concentration limitation of impurity B in the source and drain of germanium and silicon, compared with NMOS, the contact resistance of PMOS is reduced rate is more challenging. [0003] The above information disclosed in the Background section is only to enhance the understanding of the background of the technology described herein, therefore, the Background may contain certain information which is not forme...

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Problems solved by technology

[0004] The main purpose of this application is to provide a semiconductor device and its fabrication method to solve the problem of high contact resistivity of PMOS in the prior art

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