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A 10 Gigabit network controller and control method supporting time-triggered Ethernet

A network controller and time-triggered technology, which is applied in the direction of forward error control, adjustment of transmission mode, time division multiplexing system, etc., can solve the problem of affecting the clock synchronization accuracy, does not involve the specific design of the MAC controller, and does not support 10,000 Mega data transmission and other issues, to achieve the effect of reducing the average frame interval and ensuring the accuracy of network clock synchronization

Active Publication Date: 2021-07-27
XIAN MICROELECTRONICS TECH INST
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Problems solved by technology

[0004] It can be seen from the existing TTE-related patents and TTE-related documents that the existing TTE systems are implemented based on standard Gigabit Ethernet, do not support 10-Gigabit data transmission, and do not involve the specific design of the MAC controller. The protocol in the MAC layer The processing process of control frame (PCF) data is transparent to the designer, and the delay generated in the processing process cannot be dynamically recorded, which affects the clock synchronization accuracy to a certain extent

Method used

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  • A 10 Gigabit network controller and control method supporting time-triggered Ethernet

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Embodiment Construction

[0031] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0032] The technical solution of the invention is a ten-gigabit network control method supporting time-triggered Ethernet, which is used to design a ten-gigabit time-triggered Ethernet MAC controller, and is convenient for constructing a ten-gigabit time-triggered Ethernet end system or switch equipment.

[0033] The invention complies with IEEE802.3-2012 standard protocol specifications; supports XGMII interface with 64bits data bit width of 8 data channels; the interface working clock frequency is 156.25MHz; supports full-duplex data communication; The method of inserting idle characters based on the DIC algorithm to control the frame interval; support PCF frame encapsulation and PCF transparent clock update; support multi-priority data transmission scheduling; support CRC32 check and error management; support internal self-loop of XGMII int...

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Abstract

The invention discloses a 10G network controller and a control method supporting time-triggered Ethernet. The controller includes a sending channel and a receiving channel connected to a self-loop control module, and the self-loop control module is used to transmit the data stream of the sending channel To the receiving channel, the sending channel is used to frame the PCF frame, TT frame and ET frame according to the standard frame format required by the protocol and send it; the receiving channel is used to synchronize the data frame received from the physical layer with the clock, and then perform Frame analysis, and then according to the result of frame analysis, classify and store data frames into the buffer for receiving interface; support full-duplex data communication; support maximum data packet is 1518 bytes; support CRC32 check and error management; support internal XGMII interface Self-loop; support flow control function; support standard MDIO PHY management interface function.

Description

technical field [0001] The invention belongs to the technical field of backbone network bus communication of avionics systems and weapon equipment systems, and in particular relates to a 10 Gigabit rate Ethernet data link layer control method based on a time-triggered architecture. Background technique [0002] With the rapid development of aerospace electronic information systems and the continuous improvement of weapon equipment informatization, the gigabit transmission bandwidth of the existing time-triggered Ethernet (Time-Triggered Ethernet, TTE) system is no longer suitable for massive data real-time in the equipment backbone network. transmission. [0003] An FPGA-based Gigabit TTE terminal system controller (Chinese patent CN106773928) adopts a standard Gigabit Ethernet MAC controller and PHY circuit in compliance with the IEEE802.3 protocol specification, and its FPGA circuit design does not include the specific design of the MAC layer , The MAC layer and the PHY l...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L1/00H04J3/06
CPCH04J3/0635H04L1/0008H04L1/004H04L1/0083H04L2212/00
Inventor 刘扬唐金锋徐丹妮哈云雪
Owner XIAN MICROELECTRONICS TECH INST
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