81results about How to "Guaranteed synchronization accuracy" patented technology

The invention discloses a method and a device for synchronizing information distribution of a clock in the Ethernet. According to the method, by means of a neighborhood management module of each network element and according to a network element identification, a neighborhood table of each network element is established, a clock source information management module sends a clock identification and clock quality information which are produced by a clock source to the neighborhood network elements in the neighborhood table, clock source information data banks of the network elements are established, and a clock source effective path calculating module calculates synchronous paths of the network elements according to information in the clock source information data banks so that the synchronous paths of the clock source to the network elements are obtained; and when the network topology changes or the clock source can not be used, a path switching module and a clock switching module perform recalculation to obtain new synchronous paths of the network elements. According to the method and the device for synchronizing information distribution of the clock in the Ethernet, clock ring formation can be effectively prevented, and synchronization accuracy of a synchronizing network is guaranteed.

Disclosed in the embodiments of the present invention are a method and device for clock synchronization. The method comprises the following steps: slave clock equipment simultaneously carries out protocol message interactions with multiple clock source equipment , and respectively computes the time and frequency deviation with each clock source equipment according to the protocol message interaction with the multiple clock source equipment to lock the multiple clock source equipment; the slave clock equipment selects a primary clock source from the multiple clock source equipment, and corrects self time and frequency according to the time and frequency deviation with the primary clock source. According to the embodiments of the present invention, the clock source equipment is immediately locked as soon as being discovered rather than starts to be locked after being switched, so that the multiple clock source equipment is simultaneously locked by the slave clock equipment, and when the clock source equipment switching occurs, the clock source equipment is switched into the currently locked clock source equipment, and therefore, the synchronization accuracy of the time and frequency during switching can be ensured to the maximum extent, the switching speed of the clock source equipment is accelerated and switching performance is enhanced.

A dual output shaft motor based shear plate synchronous control hydraulic system relates to a plate shear synchronous control hydraulic system. The dual output shaft motor based shear plate synchronous control hydraulic system comprises two shear cylinders, two stock stopping cylinders, three pressing cylinders and a shear cylinder synchronous control system, wherein the shear cylinder synchronous control system comprises an oil tank, two same hydraulic pumps, a dual output shaft motor for driving the two hydraulic pumps to rotate, and two first check valves; an oil outlet of each first one-way valve is connected with a first oil way, a second oil way and a third oil way respectively, the first oil way comprises a pilot operated compound relief valve and a two-position two-way electromagnetic valve, the second oil way comprises a sequence valve and a two-position four-way electromagnetic valve, the third oil way comprises a reducing valve, a second check valve and a first energy accumulator, the dual output shaft motor drives the two same hydraulic pumps to supply oil for the two same shear cylinders, so as to better guarantee the synchronous accuracy of the two shear cylinders, and the two shear cylinders are respectively connected with the first energy accumulator to maintain the pressure.

Disclosed are a method of and system for providing time synchronization among first and second computer systems, where each of the computer systems includes hardware, operating system software and a layer of microcode operating between said hardware and said software. The method comprises the steps of using the microcode of the first computer system to provide a first timestamp, using the microcode of the second computer system to provide a second timestamp and a third timestamp, and using the microcode of the first computer system to provide a fourth timestamp. The method comprises the further steps of using the first, second, third and fourth timestamps to determine a timing difference between the first and second computer systems, and adjusting the timing among said first and second computer systems on the basis of said determined timing difference. Preferably, the first and second computer systems are connected together by a point-to-point link; and the first timestamp is sent from the first computer system to the second computer system, and the second and third timestamps are sent from the second computer system to the first computer system over that point-to-point link.

The invention relates to the technical field of engineering machinery, and discloses a synchronous drive control system, which comprises a hydraulic pump, a change valve, and a first double rod cylinder and a second double rod cylinder which have the same capacity. The oil inlet of the hydraulic pump is communicated with an oil tank, while the oil outlet is communicated with the oil inlet of the change valve; the first oil outlet of the change valve is communicated with a left cavity of the first double rod cylinder; a right cavity of the first double rod cylinder is communicated with a left cavity of the second double rod cylinder; a right cavity of the second double rod cylinder is communicated with the second oil outlet of the change valve; and the return port of the change valve is communicated with the oil tank. The synchronous drive control system can realize synchronous action of two cylinders, and has the advantages of simple structure, small influence by external load and low cost. The invention also discloses engineering machinery provided with the synchronous drive control system.

The invention discloses a driver for synchronous control of multiple motors, which aims to provide a driver for synchronous control of the multiple motors which can effectively reduce the weight and the size of the motor driver and can simultaneously or separately control steering and speed of multiple DC motors without programming. The invention is realized by the following technical solution: aCPU circuit board provides four working mode selections of an analog input mode, an R/C input mode, a simple serial port mode and a packet serial port mode for a driving circuit board; an analog quantity acquisition module in the CPU circuit board acquires the motor position, the current and the rotation speed information of the drive circuit board through a motor control interface module. A complex programmable logic device CPLD performs logic transformation on various input/output discrete quantities. A DSP module and a CPLD interface acquire/transmit logic signals, analyze and process RS422communication module in an RS422 communication module, control the motor control circuit to operate, and output control information to the drive circuit board to control the motor to operate according to predetermined parameters.

The invention discloses a GPS synchronous IRIG-B time code generator, which comprises a GPS receiver, a singlechip, a direct current B code generating circuit and a direct current code to alternating code switching circuit. The direct current B code generating circuit generates direct current B codes and 1 kHz square wave signal P1k which is synchronous with a second pulse signal, the direct current code to alternating code switching circuit performs low-pass filtering and phase-shifting correcting treatments on the square wave signal P1K to obtain a 1 kHz sinusoidal carrier having same frequency and phase with the square wave signal P1K, and the direct current B codes are used for performing amplitude modulation on the sinusoidal carrier to obtain alternating current B codes. The GPS synchronous IRIG-B time code generator obtains high-precision direct current B codes by adopting a hardware synchronization frequency division technique and generates high-precision alternating current B codes by adopting filtering, phase correction and amplitude modulation techniques and the complete device has a simple structure and is easy for popularization and application.

The invention relates to a synchronization method and synchronization device for the data acquisition of a merge unit for an intelligent substation. The method includes the following steps that: when the ADC (analog-to-digital converter) plug-in of the merging unit receives synchronization information sent by a CPU plug-in, a local time stamp is generated through a thermostatic crystal oscillator, wherein the local time stamp is named as an ADC (analog-to-digital converter) local time stamp; and when the synchronization information received by the ADC plug-in is invalid, self-timekeeping counting is carried out according to the ADC local time stamp. The device includes a CPU plug-in and an ADC plug-in; the CPU plug-in comprises a synchronization information generation module and a synchronization information sending module; the ADC plug-in comprises a synchronization information analysis module and a synchronization timekeeping module; and the CPU plug-in is communication connection with the ADC plug-in. According to the synchronization method and synchronization device for the data acquisition of the merge unit for the intelligent substation of the invention, self-timekeeping counting can be carried out according to synchronization time under a condition that sampling pulses are burred or lost due to interference, and therefore, sampling data error or loss in a short term can be avoided, and the stability and reliability of sampling are enhanced with cost not increased.

The invention provides an astronomical integrated navigation system data communication and processing method. Sampled data of different sensors are kept in whole-second alignment, data are synchronously collected, and data communication and data processing of all unit modules of the astronomical integrated navigation system are achieved through the FPGA.It is guaranteed that data communication between the navigation processor and each sensor module is real-time and accurate, the data communication state can be monitored, and long-time synchronization and accuracy are guaranteed. According to the invention, the synchronization accuracy of long-time work of the system is ensured.The state of each sensor module and the availability of data are monitored in real time, a basis is provided for subsequent high-precision integrated navigation.Navigation processor resources are saved.The read data is ensured to be complete and effective, data verification does not need to be conducted repeatedly, and certain fault-tolerant capacity of the astronomical integrated navigation system is provided.

The invention discloses a loading experimental bench of a synchronous jacking device, which comprises a console with a pump station module (7) and a parameter display device and four twin-jack test devices which are connected with the synchronous jacking device, and the console is connected with at least four twin-jack test devices. The loading experimental bench of the synchronous jacking devicehas high detection precision and high accuracy of the detection data.

The invention relates to the field of mobile antennas, and provides a transmission device and an electrically-tunable antenna. The device comprises a transmission assembly. The transmission assembly comprises first bevel gears, second bevel gears, a transmission shaft, gears and racks. The first bevel gears are meshed with the second bevel gears, the first bevel gears are used for being connectedwith an external driving mechanism, the second bevel gears and the gears are connected to the transmission shaft in a sleeving mode, the gears and the racks are more than one and are arranged in a one-to-one correspondence mode and meshed with one another, and each rack is used for being fixedly connected with a movable medium of a phase shifter. According to the transmission device, the rotationdirection of transmission is changed through cooperation between the first bevel gears and the second bevel gears; the plurality of gears can be arranged on the transmission shaft as required, so thatthe phases of a plurality of phase shifters can be synchronously adjusted by means of one external drive, the synchronization precision of phase adjustment is ensured, a required space can be provided for arrangement of more phase shifters, miniaturization of the antenna is facilitated, materials are reduced, and the manufacturing cost is reduced.

The invention relates to the technical field of chip cutting equipment, and provides a Y-axis precision alignment assembly and alignment method of a double-axis scribing machine, and the Y-axis precision alignment assembly comprises a compensation grating tool, an image acquisition unit and a control unit; the grating supplementing tool is arranged on the first Y axis and comprises a positioning piece, and at least one positioning mark is arranged on the positioning piece. According to the invention, the second Y axis is aligned in advance, and meanwhile, the positioning sheet of the supplementary grating tool mounted on the first Y axis is used for providing a reference for linkage stepping alignment of the first Y axis and the second Y axis; the control unit compensates the first Y axis according to the position deviation of the imaging area of the positioning mark in the first image and the first calibration area along the Y axis direction after each linkage stepping of the first Y axis and the second Y axis, so that the synchronization precision of the first Y axis and the second Y axis is ensured, and the cutting quality of the two Y axes of the double-axis scribing machine on the same workpiece at the same time is improved; because only one image acquisition unit is installed, the installation is simple and the debugging cost is low.

The invention relates to demolding process equipment used in the prefabrication process of high-speed railway ballastless track plates, in particular to a screw-type synchronous jacking automatic control track plate demolding machine. By adopting the demolding machine, the technical problem that the rhythm and strength of workers are hard to synchronize in the mode that the workers conduct demolding on track plates by manually pressing four jacks during the track plate demolding process in the prior art is solved. According to the demolding machine, is adopted; electric energy is used as a power source to be converted into mechanical energy required by the equipment in a motor and speed reducer combined structural form; unique rotating force is transmitted to the four mechanical jacks simultaneously through a transmission shaft and commutator connected structural form; while screw rods rotate, the synchronous jacking process is realized. The problem that four jacking points are not synchronous in the demolding process of track plates in the prior art is solved. The quality of track plates is guaranteed. The demolding machine is flexible, safe and reliable in operation.

The invention relates to a whole-course us-level-precision wireless ethernet synchronization apparatus of an intelligent transformer station and method thereof. The apparatus comprises a chip DP83640, an FPGA, and a constant-temperature crystal oscillator. Therefore, clock synchronization of different devices in a wireless Ethernet network without the IEEE1588 capability can be realized; and the apparatus and the method can be applied to development of various distributed electrical capacity quantity simulation and detection devices in a power system widely.

The invention discloses a fast uplink method and device of TD-SCDMA (Time Division-Synchronous Code Division Multiple Access). The device comprises a radio frequency module for converting radio frequency signals transmitted by a tested terminal into intermediate frequency baseband sampling signals, and further comprises a DDP (Digital Data Processor) module, a DSP (Digital Signal Processor) module and a MC (Master Control) module, wherein the DDP module is used for converting the intermediate frequency baseband sampling signals output by the radio frequency module into first time speed sampling signals and sending to the DSP module, and the DSP module is used for carrying out signal synchronization of the received first time speed sampling signals according to measurement instructions of the MC module and determining a first synchronous position, converting the first time speed sampling signals into second time speed sampling signals, and determining a second synchronous position in the second time speed sampling signals according to the first synchronous position. In the method and the device, the uplink synchronization accuracy of the TD-SCDMA is ensured, and simultaneously the uplink synchronization efficiency of the TD-SCDMA is improved.

This invention relates to the field of synchronizing overlay video signals with a television video signal feed, in order to allow the overlay video signals to be mixed with the television video signal feed at the proper time intervals. The synchronization is performed by using a synchronization signal which is encoded into the closed caption line of the television video signal feed.

The invention discloses a distribution line laying device, which belongs to the technical field of power construction, and comprises a base and a vertical frame. A main driving gear, a first driven gear, a first transmission wheel, a first driven pressing wheel, a second driven gear, a second transmission wheel, a second driven pressing wheel and two winding wheel supporting devices are rotationally mounted on the vertical frame; the main driving gear is driven by a motor; the first driven gear and the second driven gear are oppositely meshed with the two sides of the main driving gear, the first driven gear is coaxially and fixedly connected with the first transmission wheel, and the second driven gear is coaxially and fixedly connected with the second transmission wheel; the first drivenpressing wheel is arranged on the outer side of the first transmission wheel, and the second driven pressing wheel is arranged on the inner side of the second transmission wheel; the first driven pressing wheel and the first transmission wheel as well as the second driven pressing wheel and the second transmission wheel are used for pressing, rolling and transmitting different cables to finish wiring; and wiring operation can be synchronously carried out on various cables, the wiring efficiency is improved, tensile damage to the cables is avoided, and the power construction quality is improved.

The invention discloses a programmable anti-interference synchronizer trigger, which provides a reliable triggering signal for an analogue to digital converter (ADC) sampling system, thereby ensuring the synchronization accuracy of the sampling system. The programmable anti-interference synchronizer trigger comprises a reference point detection comparator, a positive hysteresis comparator and a negative hysteresis comparator, wherein the positive input ends of the reference point detection comparator, the positive hysteresis comparator and the negative hysteresis comparator are connected withone another, and the negative input ends of the reference point detection comparator, the positive hysteresis comparator and the negative hysteresis comparator are connected with one another; nodes of which the positive input ends are connected with one another are connected with an input signal; the output end of the reference point detection comparator is connected with a working power supply by a resistor, and is connected with a control logic circuit by a counter respectively; the output end of the positive hysteresis comparator is connected with one end of a first resistive network and the control logic circuit; the other end of the first resistive network is connected with the positive input end of the positive hysteresis comparator; the first resistive network is grounded by a grounding end, and is connected with the control logic circuit by a port; and the output end of the negative hysteresis comparator is connected with one end of a second resistive network and the control logic circuit.