An Extended Method of Parallel Bus Serial Interconnection with Error Correction and Automatic Response Mechanism

Abstract

The invention discloses a parallel bus serial interconnection expansion method with an error correction and automatic response mechanism. The CPU and multiple slave FPGAs are connected through a master FPGA. The master FPGA includes a parallel bus interface interconnected with the CPU and multiple master serial interface control circuits; each slave FPGA includes a slave serial interface control circuit inside. It is interconnected with the main FPGA in a serial manner, and interconnected with the internal circuit of the slave FPGA in a parallel bus interface; the CPU controls the work of the main serial interface control circuit through registers and memory mapping, and sends a burst command to a certain The slave serial interface circuit in the FPGA sends indirect storage access commands in the existing or custom serial communication mode. The commands include read / write operation type, operation address, read / write operation data and check code, and the slave serial interface circuit in the FPGA The serial interface control circuit receives the operation command, converts it into the same bus interface and operation sequence as the main FPGA, and performs read and write operations on the internal storage space. The invention can provide efficient, reliable, simple and strong interactive data communication between the processor and multiple FPGAs, and has high versatility.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, and is mainly used for communication between a processor (CPU) and multiple FPGAs, in particular to a parallel bus serial interconnection expansion with error correction and automatic response mechanism realized by hardware description language Method, using this technology can realize a flexible, reliable, simple, highly interactive and easy-to-expand multi-FPGA communication mode. Background technique [0002] In many applications, a processor (CPU) is required to communicate with multiple FPGAs on a single circuit board at the same time, or communicate with FPGAs distributed on different circuit boards through the backplane to work on the circuits in the FPGA Configuration, status query and low speed data transfer. [0003] The traditional method needs to use at least 1-level bidirectional bus driver circuit. In each FPGA, a parallel bus interface circuit needs to be used, and reg...

AI Technical Summary

Problems solved by technology

The advantage of this method is that the CPU can directly address each FPGA, and the operation mode is simple, but this method occupies a large number of FPGA pins, which will cause complex board-level wiring and backplane wiring, and affect signal integrity and bus drivers. It also has high requirements, lacks an error control mechanism, and the size of the available memory mapping space is limited by the width of the address lines in the bus

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