A kind of array substrate and manufacturing method thereof

A technology for array substrates and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, instruments, etc., and can solve problems such as poor overlap between the first metal layer and the second metal layer, and large slope angles

Active Publication Date: 2021-03-12
HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The present invention provides an array substrate and a manufacturing method thereof, so as to solve the problem of poor overlap between the first metal layer and the second metal layer due to the large slope angle of the connection hole in the existing array substrate manufacturing process

Method used

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  • A kind of array substrate and manufacturing method thereof
  • A kind of array substrate and manufacturing method thereof
  • A kind of array substrate and manufacturing method thereof

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Embodiment Construction

[0061] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0062] refer to figure 2 , which shows a flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention, which may specifically include the following steps:

[0063] In step 201, a first metal layer and an insulating layer are sequentially formed on a substrate, and the insulating layer covers the first metal layer.

[0064] Such as image 3 As shown, a substrate 31 is first provided, which can be a PI (Polyimide, polyimide) substrate or a glass substrate, and a first metal layer 32 is formed on the substrate 31 by a patterning process, and the patterning process includes a metal thin film Deposition, coating photoresist, mask exposure, development, etching, stripping photoresist...

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Abstract

The invention provides an array substrate and a manufacturing method thereof, and relates to the field of display technology. In the present invention, the first metal layer and the insulating layer are sequentially formed on the substrate, an etching barrier layer is formed on the insulating layer, and the etching barrier layer and the insulating layer are etched multiple times to form a connection hole penetrating through the insulating layer. The hole includes a plurality of sequentially connected via holes, and the slope angle of each via hole is smaller than a preset slope angle to form a second metal layer, and the second metal layer is connected to the first metal layer through the connection hole. By etching the etch barrier layer and the insulating layer multiple times, the formed connection hole includes a plurality of sequentially connected via holes, and since the thickness of the insulating layer etched away each time is small, it is ensured that the formed connection hole The slope angle of each via hole is smaller than the preset slope angle. When making the second metal layer later, it can avoid poor coverage or disconnection of the second metal layer due to the large slope angle of the connection hole, and improve the first metal layer. Poor bonding to the second metal layer.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof. Background technique [0002] With the continuous development of display technology, high-precision display technology (such as 8K display technology) has become an important development direction. In high-precision display technology, the wiring method of the array substrate is more dense, and the dense wiring method requires metal wires. The insulating layer between has better connection holes for lapping. [0003] Such as figure 1 As shown, when manufacturing the array substrate, firstly, the first metal layer 12 and the insulating layer 13 are sequentially formed on the substrate 11, and the photoresist 14 is coated on the insulating layer 13, and then the photoresist 14 is exposed and developed. A photoresist hole is formed, and the insulating layer 13 is dry-etched based on the photoresist hole to form a conn...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48H01L23/498
CPCH01L23/498H01L21/48G02F1/136227H01L27/124H01L27/1248H01L21/76804H01L23/5329G02F1/133345
Inventor 程磊磊方金钢丁录科刘军李伟周斌
Owner HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
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