Semiconductor device and formation method thereof
A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve the problem of low breakdown voltage, achieve the effect of reducing the distance, optimizing the layout area, and increasing the breakdown voltage of the off-state source and drain
Active Publication Date: 2019-06-07
YANGTZE MEMORY TECH CO LTD
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[0006] The invention provides a semiconductor device and its forming method, which are used to solve the problem of low source-drain breakdown voltage of existing MOS devices, so as to improve the electrical performance of three-dimensional memory
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[0050] Specific implementations of the semiconductor device and its forming method provided by the present invention will be described in detail below in conjunction with the accompanying drawings.
[0051] With the further development of 3D NAND memory technology to QLC (Quad-Level Cell, four-layer storage unit), how to further improve the off-state source-drain breakdown voltage of CMOS high-voltage devices without expanding the chip area is the current high-voltage device design. an important direction.
[0052] At present, the method of forming a drift region in DEMOS (Drain-Extension MOS, drain extended metal oxide semiconductor) and LDMOS (Lateral Double Diffused MOS, lateral double diffused metal oxide semiconductor) high-voltage devices is mainly used to improve the off-state source of the device. Drain breakdown voltage.
[0053] However, in the current DEMOS high-voltage devices, since the carrier movement is relatively close to the substrate surface of the source r...
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The present invention relates to the technical field of semiconductor manufacturing, especially to a semiconductor device and a formation method thereof. The semiconductor device comprises: a substrate; and a gate layer located at the surface of the substrate, wherein the substrate is internally provided with a source drift region and a drain drift region respectively distributed at two opposite side of the gate layer in a channel length direction, the drain drift region comprises a drain region and an insulation isolation region located between the drain region and the channel, and the depthof the insulation isolation region is smaller than or equal to the depth of the drain region. The semiconductor device and the formation method thereof optimize the device layout area while increasingthe OFF state source and drain breakdown voltage of the semiconductor device so that the semiconductor device can maintain the original layout size.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Among them, 3D NAND memory takes its small size and large capacity as the starting point, and the design concept of highly integrated storage units stacked in three-dimensional mode i...
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IPC IPC(8): H01L29/08H01L29/06H01L29/78H01L21/336
Inventor 王剑屏董洁琼
Owner YANGTZE MEMORY TECH CO LTD