A Capacitorless Low Dropout Linear Regulator

Abstract

The utility model relates to a non-capacitance type low-dropout linear voltage stabilizer, which belongs to the technical field of electronic circuits. Including bias circuit, operational amplifier circuit, power supply voltage sampling circuit, compensation circuit, power tube and feedback loop, the bias circuit is used to provide bias, the operational amplifier circuit processes the feedback voltage and reference voltage, and transmits the processing results For the power tube and the feedback loop, the power supply voltage sampling circuit adopts the intermediate frequency PSRR improvement technology, and the change of the power supply voltage is sampled through the fourth capacitor, so that the gate voltage of the first power tube can offset the change of the power supply voltage, and the intermediate frequency PSRR is improved; the compensation circuit passes The second capacitor makes the output directly coupled to the gate of the third PMOS tube, which has a transient enhancement effect, and at the same time, the third capacitor cuts off the feedforward path, expands the bandwidth, and improves the influence of the second capacitor; the power tube adopts auxiliary power tube and main power The method of separate control of the tubes improves the system efficiency at light loads, and at the same time reduces the gate parasitic capacitance of the main power tubes to improve system stability.

Description

technical field [0001] The invention relates to electronic circuit technology, in particular to a Capless low-dropout linear voltage regulator circuit. Background technique [0002] Linear regulators (LDOs) are widely used in electronic products due to their low operating voltage, low output noise, small size and simple application. Traditional LDOs all need external capacitors at the output to ensure that the LDO works normally in the circuit system. With the development of system-on-chip (SOC), it is required to reduce peripheral circuits as much as possible, and more and more modules are incorporated into the chip. For the SOC, if the LDO in the system integrates the capacitor on-chip, the chip area will be greatly increased; if the off-chip capacitor is used, the pins of the chip need to be increased. Therefore, in terms of the application cost of SOC and the reliability of LDO itself, designing a Capless LDO circuit has become a hot technology in LDO design today. Ho...

AI Technical Summary

Problems solved by technology

However, traditional LDOs without output capacitors are faced with multiple pressures of poor stability, PSRR and transient characteristics, which seriously affect the performance of the circuit system.

Images