a device

Abstract

The embodiment of the invention discloses a device, which belongs to the field of electronic technology. The device includes a master node and at least one slave node, the master node includes four master CPUs, a master PCH, and a first CPLD, each slave node includes four slave CPUs, a second CPLD, the first CPLD and a master PCH, and four A master CPU is electrically connected, the second CPLD in each slave node is electrically connected to four slave CPUs, and the master node is electrically connected to each slave node; the master PCH is used to generate the PMSYNC signal and the first clock signal, and Send it to the first CPLD; the first CPLD is used to send the received PMSYNC signal and the first clock signal to the four main CPUs; the second CPLD is used to receive the PMSYNC signal generated by the main PCH, obtain the second clock signal, and send the The four slave CPUs send the second clock signal, and when the first type of jump edge of the second clock signal is detected, the PMSYNC signal is sent to the four slave CPUs; the slave CPU is used for the second type of jump according to the second clock signal edge to receive the PMSYNC signal. Adopting the present invention can prevent PMSYNC signal receiving error.

Description

Technical field[0001]This application relates to the field of electronic technology, and more particularly to a device.Background technique[0002]Currently, in order to increase the processing power of the server, multiple nodes (such as two nodes) can be set in the server, where each node can include 4 central processing units, CPUs, and platform control units (Platform Controller Hub, PCH). In addition, one of the nodes can be set to the primary node, and the other node is from the node. In order to prevent the server from power failure, the memory data is often set, and the memory data is often set, where the main node includes the state synchronization signal driver, which may also include PMSync buffer from the node. .[0003]Specifically, when the power is detected, the PCH of the primary node can generate a state synchronization signal (PMSYNC signal), and the clock signal, which can be transmitted to 4 CPUs in the primary node through the PMSync buffer in the primary node, and ...

AI Technical Summary

Problems solved by technology

[0005] Based on the above processing method, the CPU in the slave node can only receive the clock signal and PMSYNC signal through multiple PMSYNC BUFFERs. Often multiple PMSYNC BUFFERs will cause transmission delays. In some cases, the delay time for the clock signal and the PMSYNC signal In this way, when the CPU of the slave node receives the PMSYNC signal according to the rising edge of the received clock signal, it will cause the rising edge of the clock signal to correspond to the transition edge of the PMSYNC signal, thus resulting in an error in receiving the PMSYNC signal

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