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How to make sonos memory

A manufacturing method and memory technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve problems such as process defects and adverse effects on memory performance, and achieve the effect of process integration

Active Publication Date: 2021-01-22
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0030] Figure 1G In the storage area 201, the surface of the semiconductor substrate 101 outside each of the first gate structures 203, that is, the surface of the source and drain regions between the outside of each of the first gate structures 203 is formed on the surface of the semiconductor substrate 101. The self-aligned metal silicide 109 is prone to produce small process defects, which will have an adverse effect on the performance of the memory

Method used

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  • How to make sonos memory
  • How to make sonos memory
  • How to make sonos memory

Examples

Experimental program
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Embodiment Construction

[0068] Such as figure 2 Shown is the flowchart of the manufacturing method of the SONOS memory of the embodiment of the present invention, as Figure 3A to Figure 3J As shown, it is a device structure diagram in each step of the manufacturing method of the SONOS memory according to the embodiment of the present invention. The SONOS memory in the manufacturing method of the SONOS memory according to the embodiment of the present invention includes a storage area 301 and a peripheral area outside the storage area 301 302, Figure 3A , the left side of the dotted line BB corresponds to the structural diagram of the storage area 301, and the right side of the dotted line BB corresponds to the structural diagram of the peripheral area 302; the storage area 301 includes a plurality of storage tubes, and the peripheral area 302 includes a plurality of peripheral MOS transistors , including the following steps:

[0069] Step 1, such as Figure 3A As shown, the first gate structure...

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Abstract

The invention discloses a method for manufacturing a SONOS memory, comprising the steps of: forming a first gate structure of a storage tube formed by superimposing an ONO layer and a polysilicon gate; grid structure. Forming the sidewall, including sub-steps: sequentially forming the fourth oxide layer, the fifth nitride layer and the sixth oxide layer; using the fourth oxide layer as a stop layer to etch the sixth oxide layer and the fifth nitride layer in sequence to form side wall. A salicide barrier layer is formed. Etching the salicide barrier layer; in the storage area, the second nitride layer of the ONO layer is used as a stop layer for the etching process of the salicide barrier layer and makes each first in the storage area The outer surface of the gate structure is protected. Salicide growth is performed. The invention can prevent the formation of salicide on the surface of the substrate between the gates of the storage area and thereby prevent the performance of the storage tube from being adversely affected.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a SONOS memory. Background technique [0002] SONOS is the abbreviation of silicon-oxide-nitride-oxide-silicon. In the manufacturing process of SONOS embedded memory, in order to ensure the smooth integration of the manufacturing process of the storage tube and the contact hole process of the peripheral non-storage tube, the During the side wall process, the ONO at the contact hole position between the storage tubes is etched clean, and the bottom of the contact hole of the storage tube and the contact hole of the non-storage tube are finally formed. The metal silicide formed on the surface of the source and drain regions on the side is prone to produce fine process defects during the formation process, which will have an adverse effect on the performance of the memory. [0003] Such as Figure 1A to Figure 1J Shown is a ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11563H01L27/11568H01L27/11573
CPCH10B43/00H10B43/30H10B43/40
Inventor 张可钢
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP