Serial communication method, device, computer equipment and storage medium

Abstract

The invention relates to a serial communication method and device, computer equipment and a storage medium. The method comprises: enabling a receiving end to obtain current filtering data output by afilter; when a preset state in the current filtering data is detected, obtaining valid data after the preset state in the current filtering data; after the effective data is received, waiting for a receiving delay time length, and acquiring next filtering data output by the filter by a receiving end; and taking the next filtering data as the current filtering data, and when a preset state in the current filtering data is detected, obtaining effective data after the preset state in the current filtering data. Data is filtered through a filter, the receiving end only needs to capture the currentfiltering data output by the filter, when the preset state in the current filtering data is detected, effective data in the current filtering data can be obtained, the data receiving duration of thereceiving end is prolonged, namely, delayed receiving is achieved, and therefore the accuracy of the data received by the receiving end can be guaranteed.

Description

technical field [0001] The present application relates to the technical field of communication, in particular to a serial communication method, device, computer equipment and storage medium. Background technique [0002] In the industrial field, serial communication is widely used, and commonly used serial communication methods include RS232, RS485, RS422, CAN and other communication methods. The main control chip used for serial communication includes single-chip microcomputer, ARM, DSP, FPGA and so on. Single-chip microcomputer, ARM and DSP generally contain hard-core serial processing module inside. The hard-core serial processing module notifies the CPU to receive the data after receiving the data, or after the CPU sends the data to the serial processing module, the serial processing module will be responsible for the data according to Sent out in order. However, FPGA generally does not have such a serial hard-core processing module, and users need to write their own p...

AI Technical Summary

Problems solved by technology

Under normal circumstances, the FPGA can normally collect the falling edge of the start bit, but because the serial communication is asynchronous, the sending end is sent first, and the receiving end may start to capture in the data area, and the falling edge of the data segment is captured. In this way, wrong data will be received, and it is possible to keep wrong reception. Similarly, when there is interference, the capture of the falling edge may be triggered by mistake, resulting in an error

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