A control method for linking multiple scalar cores into a single-core vector processing array

Abstract

The invention discloses a control method for linking a plurality of scalar cores into a single-core vector processing array, and the method comprises the steps: carrying out the linking according to acalculation task, enabling a plurality of scalar processors to become vector arrays of a single vector processor, and enabling a multi-core processor containing a plurality of vector processors to become a new vector processor after the linking; wherein the vector array is constructed in groups, a plurality of vector processors form a vector group, and the set of M vector groups is an array of vector operation parts of M vector processors of a new vector processor. The method has the advantages that differential processing can be provided for different vector elements in parallel, the vectorprocessing unit utilization rate can be increased, and the like.

Description

technical field [0001] The invention mainly relates to the field of microprocessors, in particular to a control method for linking multiple scalar processor cores into a vector processing array in a single processor core. Background technique [0002] Realistic computing tasks such as signal processing, image processing, high-performance computing, artificial intelligence and other application algorithms contain a large number of vector operations, such as filtering, matrix multiplication, matrix covariance, etc., and vector processors are usually used to provide these vector operations Efficient support. [0003] Single-core vector processors (hereinafter referred to as vector processors) often have only one set of instruction acquisition and one set of data access components inside, and one vector instruction can complete the processing of multiple vector elements at the same time, thus greatly saving the control of the processor. The overhead also greatly improves memory...

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Problems solved by technology

[0006] On the other hand, different algorithms and different algorithm parameters have various requirements for vector width, which makes it impossible for traditional vector processors to make any compromise between vector processing unit utilization and vector processing capabilities, because high vector processing unit utilization is essentially The vector width is required to be as short as possible, and the high vector processing capability essentially requires the vector width to be as wide as possible

Obviously, traditional vector processors cannot resolve the contradiction between the two

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