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Method for improving communication rate with upper computer based on plurality of USB interface chips

A technology of USB interface and communication rate, which is applied in the field of data communication between the lower computer and the upper computer, and can solve the problems of unstable communication and difficult development.

Pending Publication Date: 2019-08-20
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] Its disadvantages are: this solution needs to implement the USB communication protocol by itself, which is difficult to develop and has the characteristics of unstable communication.

Method used

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  • Method for improving communication rate with upper computer based on plurality of USB interface chips
  • Method for improving communication rate with upper computer based on plurality of USB interface chips
  • Method for improving communication rate with upper computer based on plurality of USB interface chips

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Experimental program
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Embodiment Construction

[0058] The FPGA control module uses EP4CE6F17C8, and the USB interface chip selects CH372. When the parallel port data input module comes from the acquisition module, when the sampling rate is 625K / s, one sampling point is 3 bytes of data, so the real-time transmission rate required is 1.84MB / s, and the transmission rate of CH372 can usually reach each block 330KB / S, so the transmission rate of 6 USB interface chips can reach 1.93MB / S, thus fully meeting the requirements of real-time transmission. The FPGA control module sequentially stores the collected data in 6 buffers, and then writes the data in the 6 buffers to the USB interface chip in turn. In the host computer, the data in each USB is processed by 6 sub-threads. The data is parsed, and then the data in the 6 queues are synthesized through a sub-thread to obtain a continuous digital signal with a sampling rate of 625K / S.

[0059] A method based on multiple USB interface chips to increase the communication rate with the h...

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PUM

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Abstract

The invention discloses a method for increasing the communication rate with an upper computer based on a plurality of USB interface chips, and solves the problem that the rate of a lower computer datainput module is not matched with the communication rate of the upper computer. A parallel port data input module, N USB interface chips and an upper computer multi-thread concurrent data processing program are included. The data input module is connected to the FPGA through a parallel port, the FPGA is connected to each USB interface chip through an SPI communication protocol, meanwhile, each USBinterface chip is connected to the upper computer through a USB protocol, and the upper computer multi-thread concurrent data processing program analyzes data of each USB interface chip. Through parallel transmission of a plurality of USB interface chips, the transmission rate is greatly improved, and the problem that the data input rate of a lower computer is not matched with the transmission speed of an upper computer is solved.

Description

Technical field [0001] The invention relates to the field of data communication between a lower computer and an upper computer, in particular to a method for solving the parallel transmission of a data input module and multiple USB interface chips. Background technique [0002] Because the upper computer has the characteristics of fast running speed and strong computing power, it usually sends various data generated by the lower computer to the upper computer for processing. When the data transmission rate of the lower computer is less than the data input rate, it will cause data redundancy. Besides, how to improve the communication speed with the host computer is the key to this method. [0003] In order to solve the problem of real-time transmission, an interface bus with a faster communication rate is usually used, or the USB communication protocol is implemented by oneself, and a fixed transmission mode is specified for specific data. [0004] Existing technical solution 1: [00...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F13/385G06F2213/0042
Inventor 张治国赖小松王艺璇施博文
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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