Semi-floating gate transistor of high-K/metal gate structure and preparation method thereof

Abstract

The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semi-floating gate transistor of a high-K/metal gate structure and a preparation methodthereof. The preparation method comprises the following steps: forming an N-type lightly-doped region at the upper part of a P-type substrate; etching in the lightly-doped region to form a U-shaped groove; forming gate oxide layers on the surface of the substrate and the surface of the U-shaped groove; etching the gate oxide layers; depositing a gate polycrystalline silicon layer, and performing P-type ion implantation and annealing activation on the gate polycrystalline silicon layer; etching the grid polycrystalline silicon layer; forming a high-K dielectric layer; depositing a metal gate onthe high-K dielectric layer; defining positions of a source region and a drain region, and respectively etching the metal gate, the high-K dielectric layer, the gate polysilicon layer and the gate oxide layer; growing a grid side wall; and performing self-aligned N-type ion implantation on the source region and the drain region, and performing annealing activation. Through the arrangement of thehigh-K/metal gate structure, the quantum tunneling effect of the gate dielectric layer is reduced, and the gate electric leakage of the semi-floating gate transistor and the power consumption caused by the gate electric leakage are improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semi-floating gate transistor with a high-K / metal gate structure and a preparation method thereof. Background technique [0002] As the device size continues to shrink to 45nm and below process technology, the thickness of the gate dielectric layer SiON is reduced to below 2nm, resulting in an increase in the leakage current of the device. The semiconductor industry uses the high-K dielectric material HfO 2 etc. replace SiON as the gate oxide layer to reduce the quantum tunneling effect of the gate dielectric layer, thereby effectively improving the gate leakage current and the power consumption caused by it. Semi-floating gate transistors also face the same problem as devices shrink. [0003] The semi-floating gate transistors with a polysilicon gate structure commonly studied at present have a size of 55nm and above, and the thickness of ...

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Problems solved by technology

[0003] The semi-floating gate transistors with a polysilicon gate structure commonly studied at present have a size of 55nm and above, and the thickness of the gate ox

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