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Decoding method and decoder

A decoder and decoding technology, applied in the field of decoding methods, LDPC decoding methods and decoders, can solve the problems of insufficient compression of invalid operations, high requirements on check matrix characteristics, and elimination of invalid operations, etc., to achieve The effect of reducing the duration of a single iteration, compressing invalid operations, and reducing power consumption

Active Publication Date: 2019-11-29
SHENZHEN XINZHILIAN TECH CO LTD
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AI Technical Summary

Problems solved by technology

However, in the prior art, there is still no method for removing all invalid operations. The decoder in the prior art may not compress enough invalid operations, or has high requirements on the characteristics of the parity check matrix. How to address more A general parity check matrix to further compress the proportion of invalid operations to improve the throughput rate is a technical problem that the industry needs to solve urgently

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Embodiment Construction

[0068] In order to describe the technical solution of the present invention in more detail and facilitate further understanding of the present invention, the specific implementation manners of the present invention will be described below in conjunction with the accompanying drawings. However, it should be understood that all the exemplary embodiments and their descriptions are used to explain the present invention, and do not constitute the only limitation to the present invention. At the same time, under the condition that the internal logic does not conflict, various implementation manners can be combined.

[0069] In the LDPC decoding method of the present invention, since the LDPC parity check matrix H used in the wireless protocol is composed of a z×z block matrix, the block matrix is ​​divided into two types, a zero matrix and a non-zero matrix, which are respectively represented by "-" and " P" denotes a zero matrix and a non-zero matrix, where Z denotes the expansion ...

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Abstract

The invention discloses a decoding method, which is based on a TDMP (Time Division Multiplexing Protocol) scheduling strategy, and comprises the following steps of: updating all variable nodes after updating a part of check nodes, then updating all variable nodes after updating the other part of check nodes, and repeating the process. According to the method, the operation of updating a part of check nodes is divided into a plurality of sub-operations, and the sub-operations and the operation of updating all variable nodes are organized into a two-stage assembly line, so that the utilization rate of a component decoder is improved; according to the method, control logic of an assembly line is constructed by combining parallelism degree requirements, so that all-zero pseudo blocks in a check matrix are skipped, and iteration time consumption can be reduced; particularly, the method performs row-column exchange on the check matrix to reduce the number of invalid operations, significantlyreduce the iteration time consumption and improve the throughput. The invention also discloses a decoder.

Description

technical field [0001] The present invention relates to the field of communication and the field of computer technology, and mainly relates to a decoding method, an LDPC decoding method and a decoder. Background technique [0002] LDPC (Low-density Parity-check, low-density parity-check) code is a linear block code with a sparse parity check matrix, which has excellent resistance to burst errors, bit error performance close to the Shannon limit, and easy parallelization Realization and other advantages, widely used in the current mainstream high-throughput wireless communication standard protocols, such as IEEE 802.11n / ac, LTE, DVB, etc. Judging from the development of the past few decades, LDPC decoders are developing in the direction of smaller area and higher throughput, so they are increasingly used in mobile devices that are sensitive to power consumption and area, such as mobile phones. [0003] The decoding algorithm of LDPC code is based on the parallel iterative de...

Claims

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Application Information

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IPC IPC(8): H03M13/11G06N3/04
CPCH03M13/1105H03M13/1148G06N3/044
Inventor 鲁宏涛潘攀
Owner SHENZHEN XINZHILIAN TECH CO LTD
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