Method for compressing codes of decoding module of instruction set simulator

A technology of decoding module and compression method, which is applied in the field of instruction set simulation, can solve problems such as the efficiency reduction of decoding functions, and achieve the effects of reducing code size, optimizing performance, and good application prospects

Inactive Publication Date: 2019-12-13
ZHEJIANG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During the decoding process, except for the judgment of the OP field, the judgment of other fields, such as the decoding feature seg

Method used

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  • Method for compressing codes of decoding module of instruction set simulator
  • Method for compressing codes of decoding module of instruction set simulator
  • Method for compressing codes of decoding module of instruction set simulator

Examples

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Example Embodiment

[0061] Example

[0062] Below take the same group of instructions of the decoding feature segment in the TMS320C64x instruction set simulator as an example to further illustrate the working principle and working process of the present invention:

[0063]The group has 7 instructions, and the decoding feature segments of these 7 instructions are all "110[4,2]". Since the decoding feature segments are the same, the instruction formats are also exactly the same. Record the frequency of occurrence of each instruction, sort in descending order, and obtain the order in the group. After sorting in descending order, the distribution of instructions in the group is shown in Table 1. The sorted instructions are analyzed to obtain the decoding function code block.

[0064] Table 1: Distribution of instructions after sorting

[0065] command name Sort within group command frequency CMPLT_L 1 246 AND_L 2 149 SUB_L 3 129 ADD_L 4 74 CMPEQ_L 5 ...

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Abstract

The invention discloses a method for compressing codes of a decoding module of an instruction set simulator. The method comprises the following steps: grouping all instructions according to the distribution condition of instruction decoding feature sections in an instruction set; dividing the instructions with decoding characteristic section distribution into the same group; meanwhile, the occurrence frequencies of all the instructions in the same group are accumulated to serve as the instruction frequency of the group; sorting all the groups in a descending order according to the instructionfrequencies of the groups, and sorting each instruction in the groups in a descending order according to the instruction frequencies of the instructions; generating a decoding code block of each groupaccording to the sorting result, and finally achieving the effect of compressing instructions with the same decoding feature section to the same decoding code block; and meanwhile, instruction decoding in the group is carried out according to a sequence from high to low, so that the code scale of the simulator decoding module is remarkably reduced. The method is suitable for various types of instruction sets, can remarkably reduce the bit matching frequency when the simulator analyzes the instruction, improves the operation efficiency of the simulator, and has a better application prospect.

Description

technical field [0001] The invention relates to instruction set simulation, in particular to a compression method for decoding module codes of the instruction set simulator. Background technique [0002] Because the instruction set simulator has the advantages of getting rid of the limitation of the number of hardware, the running process can be debugged, and the device status can be obtained at any time, it has been widely used in hardware simulation, chip design and other fields. [0003] The decoding module of the instruction set simulator determines the instruction type by matching the instruction operation code, and extracts the information of each feature segment according to the instruction encoding format. In practice, since an instruction set often contains hundreds of instructions, and the decoding module needs to support the identification of all instruction types, the codes of related modules are often very large and extremely complex. In addition, when the simu...

Claims

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Application Information

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IPC IPC(8): H03M7/30
CPCH03M7/6047H03M7/6058
Inventor 张凯旋蔡铭
Owner ZHEJIANG UNIV
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