Constant reducing processor capable of supporting shortening code length

A technology of processors and constants, which is applied in the effective technical field of invalid areas and unused areas, can solve the problems of increasing processing time, increasing the processing time of task context conversion, etc., achieving the effect of reducing code length and improving practical value

Inactive Publication Date: 2006-08-09
GK BRIDGE 1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, with a processor having such a constant register, there arises a problem of increasing the processing time of task context switching in the case of multitasking
That is, in order to execute multiple tasks, time-division multiplexing is performed while switching, and it is necessary to frequently perform task context switching. The task context switching is to transfer control to the operating system during the execution of the task. , save the information (context) necessary to execute the task again in a storage area such as a memory, and return the context of the task to be executed next, but since the value of the constant register is also included in the context, the task is increased Processing time for context transformations

Method used

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  • Constant reducing processor capable of supporting shortening code length
  • Constant reducing processor capable of supporting shortening code length
  • Constant reducing processor capable of supporting shortening code length

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0105] As a processor that achieves the above-mentioned first object, the processor in Embodiment 1 is characterized in that it restores it to the original A function of 1 constant.

[0106] (command format)

[0107] First, the structure of instructions decoded by this processor will be described.

[0108] This processor is a processor adopting VLIW architecture (hereinafter referred to as "VLIW processor"), which decodes and executes 32-bit fixed-length instructions.

[0109] FIG. 2(a) shows the field configuration of an instruction 50 executed by a processor related to the present invention. Figure 2(b) to Figure 2(d) show 16 command formats. Figure 2(b) shows an instruction format that can specify three operations at the same time, Figure 2(c) shows an instruction format that can specify two operations at the same time, and Figure 2(d) shows an instruction format that can specify one operation at the same time.

[0110] This instruction 50 has a length of 32 bits and co...

Embodiment 2

[0427] The processor according to Embodiment 2 will be described below. The processor according to the second embodiment is a processor that achieves the above-mentioned second object, and is characterized in that it has a function of avoiding useless operations in switching tasks back and forth by saving and restoring values ​​of constant registers only when necessary. Also, a numerical value beginning with 0b represents a binary number.

[0428] (The hardware structure of the processor)

[0429]FIG. 30 is a block diagram showing a hardware structure of a processor 500 according to the second embodiment. This processor is composed of an instruction register 510 , an instruction decoding circuit 520 , an execution unit 530 and an instruction reading unit 540 . In this figure, the peripheral circuit connected to the processor 500 is also shown, that is, the external memory 540 for saving the context and context of tasks.

[0430] The instruction reading unit 540 is composed ...

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Abstract

A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10, and a constant register control unit 32 which, when the format decoder 21 has decoded that the instruction includes a constant to be stored in the constant register 36, shifts the presently stored value in the constant register and stores the constant into the constant register.

Description

technical field [0001] The present invention relates to a microprocessor, in particular to a technique for validating invalid and unused areas generated in instructions. Background technique [0002] With the multifunctionalization and speed-up of microprocessor-applied products in recent years, the appearance of a microprocessor (hereinafter simply referred to as a "processor") capable of executing a program with high coding efficiency has been expected. That is, the emergence of a processor that does not include invalid codes or unused areas in each instruction constituting a program is expected. [0003] However, especially in fixed-length instructions like VLIW (VERY LONG INSTRUCTION WORD), it is necessary to generate invalid codes such as non-operation codes (nop codes) in the instructions. VLIW is composed of a plurality of operation fields, and in each operation field, an operation corresponding to a plurality of arithmetic units included in the processor is specifie...

Claims

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Application Information

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IPC IPC(8): G06F15/00G06F9/30G06F9/32G06F9/38G06F9/46
CPCG06F9/324G06F9/30101G06F9/30167G06F9/322G06F9/3885G06F9/461G06F9/00
Inventor 高山秀一桧垣信生田中哲也瓶子岳人铃木正人
Owner GK BRIDGE 1
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