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Data transmission method and device for memory access and on-chip communication of many-core processor

A data transmission method and a technology of a data transmission device, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems that the core can only wait, restrict the computing power of many-core processors, and have large differences in access delays, so as to achieve high-efficiency on-chip data processing. The effect of multiplexing, reducing hardware logic overhead, and improving computing power

Active Publication Date: 2020-01-17
JIANGNAN INST OF COMPUTING TECH
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Problems solved by technology

Conventionally, the core can usually use the LD / ST instruction to obtain new data one by one from different cores to achieve more data multiplexing. However, due to the large number of many-core cores, the difference in access delay between different cores is large, usually Dozens or hundreds of beats, the core can only wait before obtaining new data, which seriously restricts the computing power of many-core processors

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  • Data transmission method and device for memory access and on-chip communication of many-core processor
  • Data transmission method and device for memory access and on-chip communication of many-core processor
  • Data transmission method and device for memory access and on-chip communication of many-core processor

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Embodiment Construction

[0024] The following are specific embodiments of the present invention and in conjunction with the accompanying drawings, the technical solutions of the present invention are further described, but the present invention is not limited to these embodiments.

[0025] see figure 1 , the data transmission method for many-core processor memory access and on-chip communication in this embodiment includes the following steps:

[0026] S1: the channel instruction buffer unit acquires channel instructions issued by one or more source core processors;

[0027] S2: Extracting DMA channel instructions or RMA channel instructions from the channel instruction buffer unit;

[0028] S3: Analyze the DMA micro-access from the DMA channel instruction, and send the DMA micro-access to the memory, parse the RMA micro-access from the RMA channel instruction and send it to the target core processor;

[0029] S4: Initiate the answer word operation after obtaining the answer returned by the memory o...

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Abstract

The invention provides a data transmission method and device for memory access and on-chip communication of a many-core processor, and belongs to the field of computer architecture and processor microstructures. The data transmission method and device for memory access and on-chip communication of the many-core processor comprise the following steps that S1, a channel instruction buffer unit obtains channel instructions sent by one or more source core processors; S2, extracting a DMA channel instruction or an RMA channel instruction from a channel instruction buffer unit; S3, analyzing the DMAmicro-access from the DMA channel instruction, sending the DMA micro-access to a memory, analyzing the RMA micro-access from the RMA channel instruction, and sending the RMA micro-access to a targetcore processor; and S4, acquiring a response returned by the memory or a response returned by the target core processor, and then initiating an answer word operation. According to the invention, the hardware logic overhead is reduced, the on-chip data multiplexing is efficiently realized, and the computing power of the many-core processor is improved.

Description

technical field [0001] The invention belongs to the field of computer architecture and processor microstructure design, and relates to a data transmission method and device for many-core processor memory access and on-chip communication. Background technique [0002] With the development of semiconductor technology, the integration of chips is getting higher and higher. Many-core processors usually integrate hundreds of cores. Compared with traditional processors using main memory + multi-level CACHE structure, quite a few many-core processors use a storage hierarchy of main memory + on-chip local memory. For this kind of many-core processors, it is necessary for the programmer to explicitly control the data transfer between the main memory and the local memory, and to perform calculation operations while the data is being transferred. Therefore, it is necessary to use DMA technology for data transfer between the main memory and the on-chip local memory. . Compared with th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28
Inventor 施晶晶唐勇谢军张清波陈芳园陈庆强过锋
Owner JIANGNAN INST OF COMPUTING TECH
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