Neural network compiler architecture and compiling method

A neural network and compiler technology, applied in neural architecture, biological neural network model, code compilation, etc., can solve problems such as combinatorial explosion

Active Publication Date: 2020-02-07
XILINX INC
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Problems solved by technology

If you need to optimize M front-end deep learning frameworks and map them to N back-end hardware platforms, you will face O(M*N) workload and risk of combination explosion.

Method used

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  • Neural network compiler architecture and compiling method
  • Neural network compiler architecture and compiling method
  • Neural network compiler architecture and compiling method

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Embodiment Construction

[0039] Hereinafter, preferred embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] Artificial intelligence has developed rapidly in recent years, and has achieved good application effects in the fields of image classification, detection, video and voice processing, and still has great development prospects. Neural network is the core of artificial intelligence applications, and deep learning neural network algorithm is one of the most common neural network models. The workload characte...

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Abstract

The invention provides a neural network compiler architecture and method. The compiler architecture comprises: a calculation graph construction module which is used for constructing a universal firstintermediate representation based on inputted different types of model files, wherein the first intermediate representation is in a graph form; a calculation graph optimization module which is used for carrying out graph optimization on the first intermediate representation to obtain a second intermediate representation in a graph form; and an instruction generation module which is used for carrying out scheduling optimization on the second intermediate representation to obtain a fine-grained third intermediate representation, and compiling the third intermediate representation into an instruction code executed on the hardware platform based on the hardware platform. The modules in the compiler architecture are matched with various intermediate representations with different granularitiesand attributes, so that various deep learning frameworks and rear-end hardware platforms can be handled with extremely high expandability and compatibility, and efficient and accurate code optimization capability is provided.

Description

Technical field [0001] The invention relates to the field of deep learning, in particular to a neural network compiler architecture and compilation method. Background technique [0002] Neural Network has become a research hotspot in the field of image recognition in recent years. The trained neural network model can be used in many fields such as image classification, object recognition and saliency detection. In recent years, the neural network model has shown a trend of increasing computing scale and increasing complexity. Using traditional CPU platforms, it has been unable to meet its practical requirements. Therefore, the use of FPGA, GPU and other heterogeneous computing platforms for neural network accelerator design has become a new research focus. Among them, compared to the GPU platform, FPGA can achieve a higher computing energy efficiency ratio. At the same time, the FPGA's characteristics of rapid iteration and hardware reconstruction are more suitable for the requ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G06N3/04G06F8/41
CPCG06N3/063G06F8/41G06N3/045Y02D10/00
Inventor 隋凌志刘鑫王雨顺
Owner XILINX INC
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