Method for reducing heterogeneous three-dimensional network-on-chip layout power consumption

Abstract

The invention provides a method for reducing heterogeneous three-dimensional network-on-chip layout power consumption. According to a basic idea, the SLP thought of industrial engineering is applied to the field of network-on-chip layout, the power consumption of the network-on-chip layout is optimized in combination with an intelligent optimization algorithm, and the relation degree between IP cores is the highest. By comparing the power consumption of communication in different test cases with the previous power consumption, the superiority of the algorithm is verified, and the purpose of reducing the network-on-chip power consumption is achieved. Experimental results show that power consumption can be reduced by adopting a system layout optimization algorithm to solve the NoC layout planning problem, and a plurality of beneficial conclusions are obtained by analyzing and explaining experimental data. From the overall trend, the power consumption reduction amplitude is gradually reduced along with the increase of the average communication traffic between the IP cores, and when the average core communication traffic between the IP cores is within 1000Mbps, the total power consumption is averagely reduced by 40.51%.

Description

technical field [0001] The invention belongs to the interdisciplinary field of integrated circuits, intelligent optimization algorithms and industrial engineering SLP, and specifically designs a method for reducing power consumption of heterogeneous three-dimensional on-chip network layout. Background technique [0002] With the development of processors towards multi-core, more and more IPs have to be integrated on the chip, and the connections between IP cores are becoming more and more complicated. The traditional bus interconnection structure is no longer enough to meet the increasingly high Require. Therefore, it tends to gradually replace the traditional bus interconnection structure with an on-chip network with characteristics such as low power consumption and high bandwidth. [0003] According to the topological structure, the network-on-chip is divided into conventional network-on-chip and application-oriented network-on-chip. Conventional NOCs are based on a regu...

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Designers mainly rely on experience to adjust the scheme according to the constraints. Therefore, due to the different experience of different designers, the final results ...

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