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MOM capacitor, capacitor array structure and manufacturing method thereof

A technology of capacitor array and manufacturing method, which is applied in the direction of capacitors, electric solid devices, circuits, etc., can solve problems such as unfavorable structure of capacitor arrays, and achieve the effect of solving the limitation of layout design

Active Publication Date: 2020-05-08
MAXIO TECH HANGZHOU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented technology provides an improved way for making electronic devices with smaller components while maintaining their performance level or efficiency. It achieves these improvements through utilizing special materials called elec- trodes on both sides of each component's insulation layer. These elec¬roads help reduce interference from external sources like electromagnetic waves (EMI). By reducing unwanted inductive coupling between different parts within the device itself, it becomes easier to achieve better signal quality without adding extra weight or complexity.

Problems solved by technology

Technological Problem: The technical problem addressed in this patented technology relates to improving the performance of certain types of electronic devices called CMOS circuits due to their high sensitivity towards external electromagnetic interference signals. These factors affecting signal quality may lead to malfunctions caused by noise sources like radioactive rays from various radiation environments used during manufacturing processes. To address this issue, there has been developed an improved solution involving incorporating shield elements into specific areas within the device's active region where they actively prevent any unwanted effects associated with magnetic fields generated outside the chip.

Method used

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  • MOM capacitor, capacitor array structure and manufacturing method thereof
  • MOM capacitor, capacitor array structure and manufacturing method thereof
  • MOM capacitor, capacitor array structure and manufacturing method thereof

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Embodiment Construction

[0051]The present invention is described below based on examples, but the present invention is not limited to these examples. In the following detailed description of the invention, some specific details are set forth in detail. The present invention can be fully understood by those skilled in the art without the description of these detailed parts. In order to avoid obscuring the essence of the present invention, well-known methods, procedures, and flow charts are not described in detail. Additionally, the drawings are not necessarily drawn to scale.

[0052] The flowcharts and block diagrams in the accompanying drawings illustrate the possible system framework, functions and operations of the systems, methods, and devices of the embodiments of the present invention, and the blocks on the flowcharts and block diagrams can represent a module, program segment or just a segment Code, said modules, program segments and codes are all executable instructions for implementing pres...

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Abstract

The embodiment of the invention provides an MOM capacitor, a capacitor array structure and a manufacturing method thereof. The MOM capacitor includes: a substrate; a first layer, a second layer and athird layer which are sequentially arranged above the substrate in a stacked mode, a plurality of through holes used for electrically connecting the electrode strips of the first part to the first layer and the third layer to form a first electrode, and an insulating layer set between the first electrode and the second electrode, wherein the first layer and the third layer are each a polar plate,the second layer comprises a plurality of electrode strips belonging to a first part and a second part, and at least part of the electrode strips of the first part are arranged around the electrode strips of the second part, the electrode strips of the second part form a second electrode, and the polarity of the second electrode is opposite to that of the first electrode. According to the MOM capacitor and the capacitor array structure provided by the embodiment of the invention, the parasitic capacitance between the second electrode and the power ground can be remarkably reduced.

Description

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Claims

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Application Information

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Owner MAXIO TECH HANGZHOU LTD