Semiconductor package and board assembly
A semiconductor and packaging technology, applied in the field of semiconductor packaging and board assemblies
Pending Publication Date: 2020-05-12
SAMSUNG ELECTRONICS CO LTD
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- Description
- Claims
- Application Information
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[0028] Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes, sizes, etc. of components may be exaggerated or reduced for clarity.
[0029] Here, for convenience, a lower side, a lower portion, a lower surface, etc. are used to indicate a downward direction with respect to a section of the drawing, and an upper side, an upper portion, an upper surface, etc. are used to indicate a direction opposite to the downward direction. However, these directions are defined for convenience of explanation, and the claims are not specifically limited by the directions defined above, and the concepts of upper and lower are interchangeable with each other.
[0030] In the specification, the meaning of "connection" of a component to another component conceptually includes indirect connection between two components through an adhesive layer as well as direct connection between two components. In a...
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The disclosure provides a semiconductor package and a board assembly. The semiconductor package includes: a connection structure including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip having connection pads connected to the redistribution layer; an encapsulant encapsulating the semiconductor chip; firstand second pads arranged on at least one surface of the connection structure and each having a plurality of through-holes; a surface mount component disposed on the at least one surface of the connection structure and including first and second external electrodes positioned, respectively, in regions of the first and second pads; first and second connection vias arranged in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.
Description
[0001] This application claims the benefit of priority of Korean Patent Application No. 10-2018-0135129 filed in the Korean Intellectual Property Office on November 6, 2018, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] The present disclosure relates to a semiconductor package and board assembly. Background technique [0003] Recently, an important trend in technological development related to semiconductor chips has been to reduce the size of semiconductor chips. Therefore, in the field of packaging technology, as the demand for small-sized semiconductor chips and the like is rapidly increasing, it is necessary to realize a semiconductor package having a compact size while including a plurality of pins. One type of packaging technology proposed to meet the technical needs described above is the fan-out semiconductor package. [0004] Semiconductor packages may include various surface mount components, such as capacito...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L21/60H01L23/31H01L23/522H01L23/528
CPCH01L23/5226H01L23/528H01L24/02H01L23/3107H01L2224/02331H01L2224/02372H01L2224/02377H01L2224/02379H01L23/50H01L23/5389H01L23/49838H01L23/49816H01L23/3128H01L2224/12105H01L24/20H01L2924/18162H01L2224/18H01L25/16H01L2924/19106H01L2224/13111H01L2924/19105H01L2224/73204H01L2224/32225H01L2224/16227H01L24/13H01L24/16H01L24/32H01L2924/3025H01L2924/18161H01L2924/3511H01L2224/131H01L2224/13147H01L2924/0001H01L2924/01013H01L2924/01029H01L2224/16225H01L2924/00H01L2924/014H01L2924/01047H01L2924/00014H01L23/525H01L23/485H01L23/481H01L24/06H01L23/31H01L23/49822H01L2924/19102H01L23/13H01L24/24H01L2224/24265H01L23/49833
Inventor 金智勋朴美珍李镇洹
Owner SAMSUNG ELECTRONICS CO LTD