Method and system for testing system-on-chip chip

A system-on-chip and testing method technology, applied in error detection/correction, faulty computer hardware, instrument detection, etc., can solve problems such as inability to perform MCU testing, and achieve the effect of ensuring the design

Pending Publication Date: 2020-07-31
中电海康无锡科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The present invention provides a testing method of a system-on-chip and a testing system of a system-on-chip, which solves the problem that the MCU cannot be tested in the related art

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  • Method and system for testing system-on-chip chip
  • Method and system for testing system-on-chip chip

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Embodiment Construction

[0042] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0043] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments of some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0044] It should be noted that the terms "f...

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Abstract

The invention relates to the technical field of chip testing, and particularly discloses a method for testing a system-on-chip chip, which comprises the following steps of: receiving a test starting instruction of an upper computer; trimming and testing a to-be-tested chip according to the test starting instruction of the upper computer; recording a trimming test result of the chip to be tested; feeding back the trimming test result to the upper computer; and receiving a test ending instruction of the upper computer. The invention further discloses a system for testing a system-on-chip chip. The method for testing a system-on-chip chip provided by the invention not only can test and adjust the key parameters in the mass production test stage of the to-be-tested chip, but also can realize the function verification of the to-be-tested chip in the FPGA in the design stage of the to-be-tested chip, thereby ensuring that the design of a chip test mode, DFT and other test item functions is correct and errorless.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a system-on-chip testing method and a system-on-chip testing system. Background technique [0002] At present, the test of 32-bit MCU is a very critical but difficult task, mainly because the test cannot cover all functions, and the test time of a single MCU is relatively long. For the design of MCU, test technology and test cost are a challenge. The mainstream approach in the market is to design a test mode module inside the MCU, which is used to test and adjust key parameters in the mass production test phase of the chip and test the main internal key units, such as DFT (reliability test). [0003] At present, the test of 32-bit MCU mainly relies on the ATE (Automated Test Equipment) of the testing organization for testing, including mid-test and final test. The test of the MCU test mode mainly relies on the mid-test implementation. The ATE test must be tested in the ch...

Claims

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Application Information

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IPC IPC(8): G06F11/22G06F11/00G06F11/26
CPCG06F11/2205G06F11/008G06F11/26
Inventor 钱斌徐琴刘业凡孙乾程
Owner 中电海康无锡科技有限公司
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