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Quadrature clock generator and method thereof

A technology of clock generation circuit and output clock, applied in the direction of electric pulse generation, electric pulse generator circuit, pulse generation, etc., can solve the problem of signal-to-noise ratio loss

Pending Publication Date: 2020-10-09
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of the polyphase filter is that the amplitude of B1 is smaller than that of A1 due to the loss caused by the first high-pass filter composed of capacitor 111 and resistor 124
As mentioned above, smaller amplitudes result in a loss of signal-to-noise ratio

Method used

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  • Quadrature clock generator and method thereof
  • Quadrature clock generator and method thereof
  • Quadrature clock generator and method thereof

Examples

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Embodiment Construction

[0071] The present invention relates to quadrature clock generating circuits. Although the description describes several specific examples of the present invention, which relate to the preferred mode for carrying out the present invention, it should be understood that the present invention can be implemented in various ways, and is not limited to the specific examples or specific modes described below, and specific An implementation example or manner has any characteristics implemented. In other instances, well-known details have not been shown or described in order to avoid obscuring the characteristics of the invention.

[0072]Those skilled in the art should understand the terms and basic concepts related to microelectronics used in the present invention, for example, "node (circuit node)", "power supply node", "ground", "signal", "voltage", "Capacitance", "Resistance", "CMOS (Complementary Metal Oxide Semiconductor)", "PMOS (P-channel Metal Oxide Semiconductor) Transistor...

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PUM

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Abstract

Provided is quadrature clock generator and a method thereof. The method including operations of receiving an input clock at an input node, coupling the input node to a first internal node using a first capacitor, inverting a first internal signal at the first internal node into a first interim signal at a first interim node using a first inverter, coupling the first interim node to the first internal node using a first resistor, coupling the input node to a second internal node using a second resistor, inverting a second internal signal at the second internal node into a second interim signalat a second interim node using a second inverter, coupling the second interim node to the second internal node using a second capacitor, and using a buffer to receive the first interim signal and thesecond interim signal and output a first phase and a second phase of an output clock.

Description

technical field [0001] The invention relates to a quadrature clock generation technology, in particular to a circuit and method for generating a quadrature clock from a two-phase clock without using a filter. Background technique [0002] As is well known to those skilled in the art, a clock is a voltage signal that periodically switches back and forth between a low level and a high level. A biphase clock is a clock that has two phases that differ by 180 degrees. A quadrature clock is a clock with four phases, comprising a first phase, a second phase, a third phase, and a fourth phase, which are evenly spaced in time, that is, the first phase, the second phase, and the third phase 90 degrees ahead of the second phase, the third phase and the fourth phase respectively. figure 1 The shown polyphase filter 100 can be used to generate a quadrature clock from a two-phase clock, where A1 and A2 are the two phases of the two-phase clock; B1, B2, B3, and B4 are the four phases of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/02
CPCH03K3/02H03K5/1506G06F1/10H03K3/037
Inventor 林嘉亮
Owner REALTEK SEMICON CORP
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